Aleksandar Markovic 49e7e28ec9 target/mips: Correct the second argument type of cpu_supports_isa() ... "insn_flags" bitfield was expanded from 32-bit to 64-bit in commit f9c9cd63e3. However, this was not reflected on the second argument of the function cpu_supports_isa(). By chance, this did not create some wrong behavior, since the left-most halves of all instances of the second argument are currently all zeros. However, this is still a bug waiting to happen. Correct this by changing the type of the second argument to be always 64-bit. Backports commit 5b1e098128367d6ef7cb2d1e99a55fcf4fa9cdde from qemu		2019-01-25 12:45:21 -05:00
..
cp0_timer.c
cpu-qom.h	mips: MIPSCPU model subclasses	2018-03-05 00:42:29 -05:00
cpu.c	target/mips/cpu: Use type_register instead of type_register_static() in mips_cpu_register_types()	2018-09-03 17:36:23 -04:00
cpu.h	target/mips: Correct the second argument type of cpu_supports_isa()	2019-01-25 12:45:21 -05:00
dsp_helper.c
helper.c	target/mips: Implement hardware page table walker for MIPS32	2018-10-23 14:29:27 -04:00
helper.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
internal.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
lmi_helper.c
Makefile.objs
mips-defs.h	target/mips: Define a bit for MXU in insn_flags	2018-11-11 05:52:18 -05:00
msa_helper.c	target/mips: Remove floatX_maybe_silence_nan from conversions	2018-05-19 23:25:04 -04:00
op_helper.c	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
TODO	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
translate_init.c	target/mips: Disable R5900 support	2018-11-23 18:55:12 -05:00
translate.c	target/mips: Correct the second argument type of cpu_supports_isa()	2019-01-25 12:45:21 -05:00
unicorn.c
unicorn.h