| .. |
|
arm_ldst.h
|
target-arm: implement SCTLR.B, drop bswap_code
|
2018-02-21 02:08:05 -05:00 |
|
cpu64.c
|
target-arm: Add the pmceid0 and pmceid1 registers
|
2018-02-20 15:22:41 -05:00 |
|
cpu-qom.h
|
target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
|
2018-02-20 22:49:43 -05:00 |
|
cpu.c
|
target-arm: Add the pmceid0 and pmceid1 registers
|
2018-02-20 15:22:41 -05:00 |
|
cpu.h
|
arm: cpu: handle BE32 user-mode as BE
|
2018-02-21 02:12:39 -05:00 |
|
crypto_helper.c
|
target-arm: Clean up includes
|
2018-02-17 21:09:32 -05:00 |
|
helper-a64.c
|
target-arm: Move aarch64_cpu_do_interrupt() to helper.c
|
2018-02-18 22:23:06 -05:00 |
|
helper-a64.h
|
|
|
|
helper.c
|
target-arm: implement SCTLR.EE
|
2018-02-21 02:14:56 -05:00 |
|
helper.h
|
target-arm: Give CPSR setting on 32-bit exception return its own helper
|
2018-02-20 22:08:35 -05:00 |
|
internals.h
|
target-arm: Move get/set_r13_banked() to op_helper.c
|
2018-02-20 15:09:07 -05:00 |
|
iwmmxt_helper.c
|
target-arm: Clean up includes
|
2018-02-17 21:09:32 -05:00 |
|
kvm-consts.h
|
|
|
|
Makefile.objs
|
|
|
|
neon_helper.c
|
target-arm: Clean up includes
|
2018-02-17 21:09:32 -05:00 |
|
op_addsub.h
|
|
|
|
op_helper.c
|
target-arm: Raw CPSR writes should skip checks and bank switching
|
2018-02-20 22:17:48 -05:00 |
|
psci.c
|
|
|
|
translate-a64.c
|
target-arm: a64: Add endianness support
|
2018-02-21 02:31:50 -05:00 |
|
translate.c
|
target-arm: introduce disas flag for endianness
|
2018-02-21 02:20:50 -05:00 |
|
translate.h
|
target-arm: introduce disas flag for endianness
|
2018-02-21 02:20:50 -05:00 |
|
unicorn_aarch64.c
|
target-arm: Add write_type argument to cpsr_write()
|
2018-02-20 22:15:53 -05:00 |
|
unicorn_arm.c
|
target-arm: Add write_type argument to cpsr_write()
|
2018-02-20 22:15:53 -05:00 |
|
unicorn.h
|
|
|
50a3c7f2ee