James Hogan 54b349aee5 target/mips: Decode microMIPS EVA load & store instructions ... Implement decoding of microMIPS EVA load and store instruction groups in the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond() helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as opc. Backports commit 8fffc64696783b1ff1d17262d098976479895660 from qemu		2018-03-04 00:37:39 -05:00
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cpu-qom.h
cpu.c
cpu.h	target-mips: make ITC Configuration Tags accessible to the CPU	2018-03-04 00:34:30 -05:00
dsp_helper.c
helper.c	target/mips: Add CP0_Ebase.WG (write gate) support	2018-03-03 23:55:09 -05:00
helper.h	target-mips: make ITC Configuration Tags accessible to the CPU	2018-03-04 00:34:30 -05:00
lmi_helper.c
Makefile.objs
mips-defs.h
msa_helper.c
op_helper.c	target-mips: make ITC Configuration Tags accessible to the CPU	2018-03-04 00:34:30 -05:00
TODO
translate_init.c	target-mips: enable CM GCR in MIPS64R6-generic CPU	2018-03-04 00:24:09 -05:00
translate.c	target/mips: Decode microMIPS EVA load & store instructions	2018-03-04 00:37:39 -05:00
unicorn.c
unicorn.h