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Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, X86)

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Peter Maydell 56b54f361e target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions Currently the only part of an ARMCPRegInfo which is allowed to cause a CPU exception is the access function, which returns a value indicating that some flavour of UNDEF should be generated. For the ATS system instructions, we would like to conditionally generate exceptions as part of the writefn, because some faults during the page table walk (like external aborts) should cause an exception to be raised rather than returning a value. There are several ways we could do this: * plumb the GETPC() value from the top level set_cp_reg/get_cp_reg helper functions through into the readfn and writefn hooks * add extra readfn_with_ra/writefn_with_ra hooks that take the GETPC() value * require the ATS instructions to provide a dummy accessfn, which serves no purpose except to cause the code generation to emit TCG ops to sync the CPU state * add an ARM_CP_ flag to mark the ARMCPRegInfo as possibly throwing an exception in its read/write hooks, and make the codegen sync the CPU state before calling the hooks if the flag is set This patch opts for the last of these, as it is fairly simple to implement and doesn't require invasive changes like updating the readfn/writefn hook function prototype signature. Backports commit 37ff584c15bc3e1dd2c26b1998f00ff87189538c from qemu		2019-11-20 17:24:37 -05:00
bindings	Removed hardcoded CP0C3_ULRI (#1098 )	2019-08-08 20:08:57 -04:00
docs	fix invalid script path (#975 ) (#976 )	2019-02-28 17:02:06 -05:00
include	x86: setup FS & GS base	2019-08-08 20:26:45 -04:00
msvc	msvc: Define CONFIG_TCG	2019-01-30 13:52:30 -05:00
qemu	target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions	2019-11-20 17:24:37 -05:00
samples	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
tests	Add missing x86_vec regression test	2019-02-28 17:08:19 -05:00
.appveyor.yml
.gitignore	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
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AUTHORS.TXT
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config.mk
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COPYING_GLIB
COPYING.LGPL2
CREDITS.TXT	Adding Philippe Antoine to CREDITS	2018-10-06 04:50:10 -04:00
install-cmocka-linux.sh
list.c
make.sh	remove broken iOS builds (#1109 )	2019-08-08 20:09:05 -04:00
Makefile	uc: Restore armeb target	2019-04-19 15:29:25 -04:00
msvc.bat
pkgconfig.mk
README.md
uc.c	uc: Restore armeb target	2019-04-19 15:29:25 -04:00
windows_export.bat

README.md

Unicorn Engine

Unicorn is a lightweight, multi-platform, multi-architecture CPU emulator framework based on QEMU.

Unicorn offers some unparalleled features:

Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, SPARC, and X86 (16, 32, 64-bit)
Clean/simple/lightweight/intuitive architecture-neutral API
Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal and Haskell.
Native support for Windows & *nix (with Mac OSX, Linux, *BSD & Solaris confirmed)
High performance via Just-In-Time compilation
Support for fine-grained instrumentation at various levels
Thread-safety by design
Distributed under free software license GPLv2

Further information is available at http://www.unicorn-engine.org

License

This project is released under the GPL license.

Compilation & Docs

See docs/COMPILE.md file for how to compile and install Unicorn.

More documentation is available in docs/README.md.

Contact

Contribute

If you want to contribute, please pick up something from our Github issues.

We also maintain a list of more challenged problems in a TODO list.

CREDITS.TXT records important contributors of our project.