ShihPo Hung 7fffc5208c target/riscv: update mstatus.SD when FS is set dirty ... remove the check becuase SD bit should summarize FS and XS fields unconditionally. Backports commit 82f014671cf057de51c4a577c9e2ad637dcec6f9 from qemu		2020-03-21 12:22:56 -04:00
..
insn_trans	target/riscv: fsd/fsw doesn't dirty FP state	2020-03-21 12:20:52 -04:00
cpu_bits.h	target/riscv: Add the mcountinhibit CSR	2019-08-08 17:04:52 -04:00
cpu_helper.c	RISC-V: Clear load reservations on context switch and SC	2019-08-08 17:15:45 -04:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	target/riscv: rationalise softfloat includes	2019-11-18 21:17:03 -05:00
cpu.h	target/riscv: rationalise softfloat includes	2019-11-18 21:17:03 -05:00
csr.c	RISC-V: Add support for the Zicsr extension	2019-08-08 17:10:34 -04:00
fpu_helper.c	target/riscv: rationalise softfloat includes	2019-11-18 21:17:03 -05:00
helper.h
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode
insn32.decode
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
Makefile.objs	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
op_helper.c	riscv: Set xPIE to 1 after xRET	2020-03-21 12:18:59 -04:00
pmp.c	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	2019-08-08 16:55:52 -04:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-08-08 16:52:57 -04:00
translate.c	target/riscv: update mstatus.SD when FS is set dirty	2020-03-21 12:22:56 -04:00
unicorn.c
unicorn.h