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https://github.com/yuzu-emu/unicorn.git
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59865351e0
CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Backports commit e117f52636d04502fab28bd3abe93347c29f39a5 from qemu |
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.. | ||
default-configs | ||
docs | ||
fpu | ||
hw | ||
include | ||
qapi | ||
qobject | ||
qom | ||
scripts | ||
target-arm | ||
target-i386 | ||
target-m68k | ||
target-mips | ||
target-sparc | ||
tcg | ||
util | ||
aarch64.h | ||
aarch64eb.h | ||
accel.c | ||
arm.h | ||
armeb.h | ||
CODING_STYLE | ||
configure | ||
COPYING | ||
COPYING.LIB | ||
cpu-exec.c | ||
cpus.c | ||
cputlb.c | ||
exec.c | ||
gen_all_header.sh | ||
glib_compat.c | ||
HACKING | ||
header_gen.py | ||
ioport.c | ||
LICENSE | ||
m68k.h | ||
Makefile | ||
Makefile.objs | ||
Makefile.target | ||
memory_mapping.c | ||
memory.c | ||
mips64.h | ||
mips64el.h | ||
mips.h | ||
mipsel.h | ||
powerpc.h | ||
qapi-schema.json | ||
qemu-log.c | ||
qemu-timer.c | ||
rules.mak | ||
softmmu_template.h | ||
sparc64.h | ||
sparc.h | ||
tcg-runtime.c | ||
translate-all.c | ||
translate-all.h | ||
unicorn_common.h | ||
VERSION | ||
vl.c | ||
vl.h | ||
x86_64.h |