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Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, X86)

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Artyom Tarasenko 59ec6876bd target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are allowed with these ASIs. Backports commit 3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8 from qemu		2018-03-01 22:29:21 -05:00
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README.md

Unicorn Engine

Unicorn is a lightweight, multi-platform, multi-architecture CPU emulator framework based on QEMU.

Unicorn offers some unparalleled features:

Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, SPARC, and X86 (16, 32, 64-bit)
Clean/simple/lightweight/intuitive architecture-neutral API
Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal and Haskell.
Native support for Windows & *nix (with Mac OSX, Linux, *BSD & Solaris confirmed)
High performance via Just-In-Time compilation
Support for fine-grained instrumentation at various levels
Thread-safety by design
Distributed under free software license GPLv2

Further information is available at http://www.unicorn-engine.org

License

This project is released under the GPL license.

Compilation & Docs

See docs/COMPILE.md file for how to compile and install Unicorn.

More documentation is available in docs/README.md.

Contact

Contribute

If you want to contribute, please pick up something from our Github issues.

We also maintain a list of more challenged problems in a TODO list.

CREDITS.TXT records important contributors of our project.