mirror of
https://github.com/yuzu-emu/unicorn.git
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b6f752970b
This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include <string.h>
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "hw/riscv/spike.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "unicorn_common.h"
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#include "uc_priv.h"
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#ifdef TARGET_RISCV32
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const int RISCV32_REGS_STORAGE_SIZE = offsetof(CPURISCVState, tlb_table);
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#else
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const int RISCV64_REGS_STORAGE_SIZE = offsetof(CPURISCVState, tlb_table);
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#endif
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static void riscv_release(void *ctx) {
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TCGContext *tcg_ctx = (TCGContext *) ctx;
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release_common(ctx);
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g_free(tcg_ctx->tb_ctx.tbs);
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}
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static void riscv_reg_reset(struct uc_struct *uc) {
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CPUArchState *env = uc->cpu->env_ptr;
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memset(env->gpr, 0, sizeof(env->gpr));
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memset(env->fpr, 0, sizeof(env->fpr));
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env->priv = PRV_M;
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env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
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env->mcause = 0;
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env->pc = env->resetvec;
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set_default_nan_mode(1, &env->fp_status);
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}
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static int riscv_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count) {
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CPUState *const cs = uc->cpu;
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CPURISCVState *const state = &RISCV_CPU(uc, cs)->env;
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for (int i = 0; i < count; i++) {
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const unsigned int reg_id = regs[i];
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void *const value = vals[i];
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if (reg_id >= UC_RISCV_REG_X0 && reg_id <= UC_RISCV_REG_X31) {
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memcpy(value, &state->gpr[reg_id - UC_RISCV_REG_X0], sizeof(state->gpr[0]));
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} else if (reg_id >= UC_RISCV_REG_F0 && reg_id <= UC_RISCV_REG_F31) {
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memcpy(value, &state->fpr[reg_id - UC_RISCV_REG_F0], sizeof(state->fpr[0]));
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} else if (reg_id == UC_RISCV_REG_PC) {
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memcpy(value, &state->pc, sizeof(state->pc));
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}
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}
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return 0;
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}
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static int riscv_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count) {
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CPUState *const cs = uc->cpu;
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CPURISCVState *const state = &RISCV_CPU(uc, cs)->env;
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for (int i = 0; i < count; i++) {
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const unsigned int reg_id = regs[i];
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const void *value = vals[i];
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// Intentionally exclude the zero register (X0) in the lower-bound
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if (reg_id > UC_RISCV_REG_X0 && reg_id <= UC_RISCV_REG_X31) {
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memcpy(&state->gpr[reg_id - UC_RISCV_REG_X0], value, sizeof(state->gpr[0]));
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} else if (reg_id >= UC_RISCV_REG_F0 && reg_id <= UC_RISCV_REG_F31) {
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memcpy(&state->fpr[reg_id - UC_RISCV_REG_F0], value, sizeof(state->fpr[0]));
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} else if (reg_id == UC_RISCV_REG_PC) {
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memcpy(&state->pc, value, sizeof(state->pc));
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc_emu_stop(uc);
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}
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}
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return 0;
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}
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static void riscv_set_pc(struct uc_struct *uc, uint64_t address) {
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CPURISCVState *state = uc->cpu->env_ptr;
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state->pc = address;
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}
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static bool riscv_stop_interrupt(int int_no) {
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switch(int_no) {
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default:
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return false;
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}
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}
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DEFAULT_VISIBILITY
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#ifdef TARGET_RISCV32
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void riscv32_uc_init(struct uc_struct *uc) {
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#else
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void riscv64_uc_init(struct uc_struct *uc) {
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#endif
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register_accel_types(uc);
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riscv_cpu_register_types(uc);
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spike_v1_10_0_machine_init_register_types(uc);
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uc->release = riscv_release;
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uc->reg_read = riscv_reg_read;
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uc->reg_write = riscv_reg_write;
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uc->reg_reset = riscv_reg_reset;
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uc->set_pc = riscv_set_pc;
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uc->stop_interrupt = riscv_stop_interrupt;
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uc_common_init(uc);
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}
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