unicorn/qemu
Peter Maydell 62178626e4 target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
Our current usage of the isar_feature feature tests almost always
uses an _aa32_ test when the code path is known to be AArch32
specific and an _aa64_ test when the code path is known to be
AArch64 specific. There is just one exception: in the vfp_set_fpscr
helper we check aa64_fp16 to determine whether the FZ16 bit in
the FP(S)CR exists, but this code is also used for AArch32.
There are other places in future where we're likely to want
a general "does this feature exist for either AArch32 or
AArch64" check (typically where architecturally the feature exists
for both CPU states if it exists at all, but the CPU might be
AArch32-only or AArch64-only, and so only have one set of ID
registers).

Introduce a new category of isar_feature_* functions:
isar_feature_any_foo() should be tested when what we want to
know is "does this feature exist for either AArch32 or AArch64",
and always returns the logical OR of isar_feature_aa32_foo()
and isar_feature_aa64_foo().

Backports commit 6e61f8391cc6cb0846d4bf078dbd935c2aeebff5 from qemu
2020-03-21 18:12:02 -04:00
..
accel Ensure that PC is not fixed up when code tracing or timing. (#1179) 2020-01-14 09:52:25 -05:00
crypto
default-configs target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
docs
fpu fpu: rename softfloat-specialize.h -> .inc.c 2019-11-18 21:12:30 -05:00
hw Expose different 32-bit ARM CPU models to users via UC_MODE flags (#1165) 2020-01-14 09:37:21 -05:00
include tcg: Add support for a helper with 7 arguments 2020-03-21 16:53:56 -04:00
qapi
qobject
qom cpu: Move icount_decr to CPUNegativeOffsetState 2019-06-13 15:34:28 -04:00
scripts decodetree: Suppress redundant declaration warnings 2019-11-18 21:21:30 -05:00
target target/arm: Add isar_feature_any_fp16 and document naming/usage conventions 2020-03-21 18:12:02 -04:00
tcg tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
util util/cutils: Turn FIXME comment into QEMU_BUILD_BUG_ON() 2020-01-14 08:04:30 -05:00
aarch64.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
aarch64eb.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
accel.c
arm.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
armeb.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
CODING_STYLE.rst docs: split the CODING_STYLE doc into distinct groups 2019-11-28 02:54:44 -05:00
configure configure: Require Python >= 3.5 2020-01-14 08:09:23 -05:00
COPYING
COPYING.LIB
cpus.c
exec.c Memory: Enable writeback for given memory region 2020-01-14 07:44:24 -05:00
gen_all_header.sh
glib_compat.c target/arm: Add VHE system register redirection and aliasing 2020-03-21 15:57:03 -04:00
header_gen.py tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
ioport.c
LICENSE
m68k.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
Makefile Makefile: Rename targets for make recursion 2019-08-08 17:26:49 -04:00
Makefile.objs
Makefile.target
memory_ldst.inc.c memory: Single byte swap along the I/O path 2020-01-07 19:12:04 -05:00
memory_mapping.c
memory.c Memory: Enable writeback for given memory region 2020-01-14 07:44:24 -05:00
mips64.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
mips64el.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
mips.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
mipsel.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
powerpc.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
qemu-timer.c
riscv32.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
riscv64.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
rules.mak
sparc64.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
sparc.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
unicorn_common.h
VERSION Open 5.0 development tree 2020-01-07 17:50:51 -05:00
vl.c
vl.h
x86_64.h tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00