unicorn/qemu
Richard Henderson 66e6bea084
tcg: Add INDEX_op_dupm_vec
Allow the backend to expand dup from memory directly, instead of
forcing the value into a temp first. This is especially important
if integer/vector register moves do not exist.

Note that officially tcg_out_dupm_vec is allowed to fail.
If it did, we could fix this up relatively easily:

VECE == 32/64:
Load the value into a vector register, then dup.
Both of these must work.

VECE == 8/16:
If the value happens to be at an offset such that an aligned
load would place the desired value in the least significant
end of the register, go ahead and load w/garbage in high bits.

Load the value w/INDEX_op_ld{8,16}_i32.
Attempt a move directly to vector reg, which may fail.
Store the value into the backing store for OTS.
Load the value into the vector reg w/TCG_TYPE_I32, which must work.
Duplicate from the vector reg into itself, which must work.

All of which is well and good, except that all supported
hosts can support dupm for all vece, so all of the failure
paths would be dead code and untestable.

Backports commit 37ee55a081b7863ffab2151068dd1b2f11376914 from qemu
2019-05-16 15:38:02 -04:00
..
accel cputlb: Do unaligned store recursion to outermost function 2019-05-14 07:45:15 -04:00
crypto
default-configs target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
docs
fpu qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
hw target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
include osdep: Fix mingw compilation regarding stdio formats 2019-05-09 17:44:14 -04:00
qapi
qobject
qom tcg: Add CPUState cflags_next_tb 2019-05-04 22:30:22 -04:00
scripts decodetree: Add DisasContext argument to !function expanders 2019-05-09 17:40:45 -04:00
target tcg: Specify optional vector requirements with a list 2019-05-16 15:05:02 -04:00
tcg tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
util util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64 2019-05-09 17:43:27 -04:00
aarch64.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
aarch64eb.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
accel.c
arm.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
armeb.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
CODING_STYLE
configure configure: automatically pick python3 is available 2019-05-03 11:36:36 -04:00
COPYING
COPYING.LIB
cpus.c
exec.c exec.c: refactor function flatview_add_to_dispatch() 2019-03-11 17:00:46 -04:00
gen_all_header.sh
glib_compat.c target/arm/translate: Synchronize with Qemu 2019-04-27 10:13:01 -04:00
HACKING
header_gen.py tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
ioport.c
LICENSE
m68k.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
Makefile config-all-devices.mak: rebuild on reconfigure 2019-03-29 19:31:32 -04:00
Makefile.objs
Makefile.target
memory_ldst.inc.c
memory_mapping.c
memory.c cputlb: Synchronize with qemu 2019-04-26 15:48:45 -04:00
mips64.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
mips64el.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
mips.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
mipsel.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
powerpc.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
qemu-timer.c
riscv32.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
riscv64.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
rules.mak
sparc64.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
sparc.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
unicorn_common.h
VERSION Open 4.1 development tree 2019-04-24 11:59:00 -04:00
vl.c
vl.h
x86_64.h tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00