Peter Maydell 6add2f0f65 target/arm: Rename cp15.c6_rgnr to pmsav7.rnr ... Almost all of the PMSAv7 state is in the pmsav7 substruct of the ARM CPU state structure. The exception is the region number register, which is in cp15.c6_rgnr. This exception is a bit odd for M profile, which otherwise generally does not store state in the cp15 substruct. Rename cp15.c6_rgnr to pmsav7.rnr accordingly. Backports commit 8531eb4f614a60e6582d4832b15eee09f7d27874 from qemu		2018-03-04 01:18:53 -05:00
..
crypto
default-configs
docs
fpu	softfloat: define floatx80_round()	2018-03-03 20:57:27 -05:00
hw
include	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
qapi	qapi: add explicit null to string input and output visitors	2018-03-03 20:32:50 -05:00
qobject	qnum: add uint type	2018-03-03 18:37:56 -05:00
qom	qom: Fix ambiguous path detection when ambiguous=NULL	2018-03-03 22:49:21 -05:00
scripts	scripts: use build_ prefix for string not piped through cgen()	2018-03-03 22:11:28 -05:00
target	target/arm: Rename cp15.c6_rgnr to pmsav7.rnr	2018-03-04 01:18:53 -05:00
tcg	tcg/mips: reserve a register for the guest_base.	2018-03-03 23:04:55 -05:00
util	util/cacheinfo: Add missing include for ppc linux	2018-03-03 23:05:44 -05:00
aarch64.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
aarch64eb.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
accel.c
arm.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
armeb.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
atomic_template.h
CODING_STYLE
configure	build: add -Wexpansion-to-defined	2018-03-03 22:12:31 -05:00
COPYING
COPYING.LIB
cpu-exec-common.c
cpu-exec.c	tcg: Introduce goto_ptr opcode and tcg_gen_lookup_and_goto_ptr	2018-03-02 21:05:18 -05:00
cpus.c	tcg: handle EXCP_ATOMIC exception for system emulation	2018-03-02 09:56:43 -05:00
cputlb.c	tcg: consistently access cpu->tb_jmp_cache atomically	2018-03-03 21:12:36 -05:00
exec.c	Revert "exec.c: Fix breakpoint invalidation race"	2018-03-03 22:14:35 -05:00
gen_all_header.sh
glib_compat.c	qapi: Improve qobject input visitor error reporting	2018-03-02 12:05:53 -05:00
HACKING
header_gen.py	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
ioport.c
LICENSE
m68k.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
Makefile
Makefile.objs
Makefile.target	tcg: add the CONFIG_TCG into Makefiles	2018-03-03 21:39:30 -05:00
memory_ldst.inc.c
memory_mapping.c
memory.c	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
mips64.h	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
mips64el.h	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
mips.h	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
mipsel.h	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
powerpc.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
qapi-schema.json	qapi: Update scripts to commit 01b2ffcedd94ad7b42bc870e4c6936c87ad03429	2018-03-03 18:32:12 -05:00
qemu-timer.c
rules.mak
softmmu_template.h
sparc64.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
sparc.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00
tcg-runtime.c	tcg: Increase hit rate of lookup_tb_ptr	2018-03-03 17:16:23 -05:00
translate-all.c	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
translate-all.h
translate-common.c
unicorn_common.h
VERSION
vl.c	util: add cacheinfo	2018-03-03 16:58:28 -05:00
vl.h
x86_64.h	memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()	2018-03-03 22:29:01 -05:00