James Hogan 72677eadd0 target/mips: Weaken TLB flush on UX,SX,KX,ASID changes ... There is no need to invalidate any shadow TLB entries when the ASID changes or when access to one of the 64-bit segments has been disabled, since doing so doesn't reveal to software whether any TLB entries have been evicted into the shadow half of the TLB. Therefore weaken the tlb flushes in these cases to only flush the QEMU TLB. Backports commit 9658e4c342e6ae0d775101f8f6bb6efb16789af1 from qemu		2018-03-03 23:40:37 -05:00
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arm	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
i386	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
m68k	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
mips	target/mips: Weaken TLB flush on UX,SX,KX,ASID changes	2018-03-03 23:40:37 -05:00
sparc	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00