mirror of
https://github.com/yuzu-emu/unicorn.git
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7388fff079
Add support for "-cpu max" for ARM guests. This CPU type behaves like "-cpu host" when KVM is enabled, and like a system CPU with the maximum possible feature set otherwise. (Note that this means it won't be migratable across versions, as we will likely add features to it in future.) Backports commit bab52d4bba3f22921a690a887b4bd0342f2754cd from qemu
318 lines
11 KiB
C
318 lines
11 KiB
C
/*
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* QEMU AArch64 CPU
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*
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* Copyright (c) 2013 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "hw/arm/arm.h"
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#include "sysemu/sysemu.h"
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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static inline QEMU_UNUSED_FUNC void unset_feature(CPUARMState *env, int feature)
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{
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env->features &= ~(1ULL << feature);
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}
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#ifndef CONFIG_USER_ONLY
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static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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/* Number of cores is in [25:24]; otherwise we RAZ */
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return (cpu->core_count - 1) << 24;
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}
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#endif
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static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
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#ifndef CONFIG_USER_ONLY
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{ "L2CTLR_EL1", 0,11,0, 3,1,2, ARM_CP_STATE_AA64,
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0, PL1_RW, 0, NULL, 0, 0, {0, 0},
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NULL, a57_a53_l2ctlr_read, arm_cp_write_ignore, },
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{ "L2CTLR", 15,9,0, 0,1,2, 0,
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0, PL1_RW, 0, NULL, 0, 0, {0, 0},
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NULL, a57_a53_l2ctlr_read, arm_cp_write_ignore, },
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#endif
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{ "L2ECTLR_EL1", 0,11,0, 3,1,3, ARM_CP_STATE_AA64,
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ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
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{ "L2ECTLR", 15,9,0, 0,1,3, 0,
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ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
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{ "L2ACTLR", 0,15,0, 3,1,0, ARM_CP_STATE_BOTH,
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ARM_CP_CONST, PL1_RW, 0, NULL, 0 },
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{ "CPUACTLR_EL1", 0,15,2, 3,1,0, ARM_CP_STATE_AA64,
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ARM_CP_CONST, PL1_RW, 0, NULL, 0 },
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{ "CPUACTLR", 15,0,15, 0,0,0, 0,
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ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, 0, NULL, 0, },
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{ "CPUECTLR_EL1", 0,15,2, 3,1,1, ARM_CP_STATE_AA64,
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ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
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{ "CPUECTLR", 15,0,15, 0,1,0, 0,
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ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, 0, NULL, 0, },
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{ "CPUMERRSR_EL1", 0,15,2, 3,1,2, ARM_CP_STATE_AA64,
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ARM_CP_CONST, PL1_RW, 0, NULL, 0 },
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{ "CPUMERRSR", 15,0,15, 0,2,0, 0,
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ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, 0, NULL, 0 },
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{ "L2MERRSR_EL1", 0,15,2, 3,1,3, ARM_CP_STATE_AA64,
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ARM_CP_CONST, PL1_RW, 0, NULL, 0 },
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{ "L2MERRSR", 15,0,15, 0,3,0, 0,
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ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, 0, NULL, 0 },
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REGINFO_SENTINEL
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};
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static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_V8_AES);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->midr = 0x411fd070;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->mvfr0 = 0x10110222;
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cpu->mvfr1 = 0x12111111;
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cpu->mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->id_isar0 = 0x02101110;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232042;
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cpu->id_isar3 = 0x01112131;
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cpu->id_isar4 = 0x00011142;
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cpu->id_isar5 = 0x00011121;
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cpu->id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->pmceid0 = 0x00000000;
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cpu->pmceid1 = 0x00000000;
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cpu->id_aa64isar0 = 0x00011120;
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cpu->id_aa64mmfr0 = 0x00001124;
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
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}
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static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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cpu->dtb_compatible = "arm,cortex-a53";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_V8_AES);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
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cpu->midr = 0x410fd034;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->mvfr0 = 0x10110222;
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cpu->mvfr1 = 0x12111111;
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cpu->mvfr2 = 0x00000043;
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cpu->ctr = 0x84448004; /* L1Ip = VIPT */
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->id_isar0 = 0x02101110;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232042;
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cpu->id_isar3 = 0x01112131;
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cpu->id_isar4 = 0x00011142;
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cpu->id_isar5 = 0x00011121;
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cpu->id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->id_aa64isar0 = 0x00011120;
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cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
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}
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/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
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* otherwise, a CPU with as many features enabled as our emulation supports.
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* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
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* this only needs to handle 64 bits.
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*/
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static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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aarch64_a57_initfn(uc, obj, opaque);
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/* In future we might add feature bits here even if the
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* real-world A57 doesn't implement them.
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*/
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}
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// Unicorn: enabled for the general use-case as well.
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static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_V8_AES);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
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set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
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set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
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set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
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set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
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cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
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cpu->dcz_blocksize = 7; /* 512 bytes */
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}
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typedef struct ARMCPUInfo {
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const char *name;
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void (*initfn)(struct uc_struct *uc, Object *obj, void *opaque);
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void (*class_init)(struct uc_struct *uc, ObjectClass *oc, void *data);
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} ARMCPUInfo;
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static const ARMCPUInfo aarch64_cpus[] = {
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{ "cortex-a57", aarch64_a57_initfn },
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{ "cortex-a53", aarch64_a53_initfn },
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{ "max", aarch64_max_initfn },
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// Unicorn: enabled for the general use case as well
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{ "any", aarch64_any_initfn },
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{ NULL }
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};
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static QEMU_UNUSED_FUNC bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(NULL, obj);
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return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
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}
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static void aarch64_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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}
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static void aarch64_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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}
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static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
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{
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ARMCPU *cpu = ARM_CPU(cs->uc, cs);
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/* It's OK to look at env for the current mode here, because it's
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* never possible for an AArch64 TB to chain to an AArch32 TB.
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* (Otherwise we would need to use synchronize_from_tb instead.)
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*/
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if (is_a64(&cpu->env)) {
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cpu->env.pc = value;
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} else {
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cpu->env.regs[15] = value;
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}
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}
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static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(uc, oc);
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cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
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cc->set_pc = aarch64_cpu_set_pc;
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}
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static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
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{
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TypeInfo type_info = { 0 };
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type_info.parent = TYPE_AARCH64_CPU;
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type_info.instance_size = sizeof(ARMCPU);
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type_info.instance_init = info->initfn;
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type_info.class_size = sizeof(ARMCPUClass);
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type_info.class_init = info->class_init;
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type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
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type_register(uc, &type_info);
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g_free((void *)type_info.name);
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}
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void aarch64_cpu_register_types(void *opaque)
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{
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const ARMCPUInfo *info = aarch64_cpus;
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static TypeInfo aarch64_cpu_type_info = { 0 };
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aarch64_cpu_type_info.name = TYPE_AARCH64_CPU;
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aarch64_cpu_type_info.parent = TYPE_ARM_CPU;
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aarch64_cpu_type_info.instance_size = sizeof(ARMCPU);
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aarch64_cpu_type_info.instance_init = aarch64_cpu_initfn;
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aarch64_cpu_type_info.instance_finalize = aarch64_cpu_finalizefn;
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aarch64_cpu_type_info.abstract = true;
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aarch64_cpu_type_info.class_size = sizeof(AArch64CPUClass);
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aarch64_cpu_type_info.class_init = aarch64_cpu_class_init;
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type_register_static(opaque, &aarch64_cpu_type_info);
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while (info->name) {
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aarch64_cpu_register(opaque, info);
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info++;
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}
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}
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