Andrew Baumann 76cd64dd7e target/arm: implement armv8 PMUSERENR (user-mode enable bits) ... In armv8, this register implements more than a single bit, with fine-grained enables for read access to event counters, cycles counters, and write access to the software increment. This change implements those checks using custom access functions for the relevant registers. Backports commit 6ecd0b6ba0591ef280ed984103924d4bdca5ac32 from qemu		2018-03-02 12:55:46 -05:00
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arm_ldst.h	Fix Thumb-1 BE32 execution and disassembly.	2018-03-02 00:20:11 -05:00
arm-powerctl.c	ARM: Factor out ARM on/off PSCI control functions	2018-03-01 23:31:47 -05:00
arm-powerctl.h	ARM: Factor out ARM on/off PSCI control functions	2018-03-01 23:31:47 -05:00
cpu64.c	target-arm: Enable EL2 feature bit on A53 and A57	2018-03-01 23:36:44 -05:00
cpu-qom.h
cpu.c	arm: Correctly handle watchpoints for BE32 CPUs	2018-03-02 00:24:33 -05:00
cpu.h	tcg: enable MTTCG by default for ARM on x86 hosts	2018-03-02 10:32:47 -05:00
crypto_helper.c
helper-a64.c
helper-a64.h
helper.c	target/arm: implement armv8 PMUSERENR (user-mode enable bits)	2018-03-02 12:55:46 -05:00
helper.h
internals.h	arm: Correctly handle watchpoints for BE32 CPUs	2018-03-02 00:24:33 -05:00
iwmmxt_helper.c
kvm-consts.h	arm: better stub version for MISMATCH_CHECK	2018-03-02 00:13:45 -05:00
Makefile.objs	ARM: Factor out ARM on/off PSCI control functions	2018-03-01 23:31:47 -05:00
neon_helper.c
op_addsub.h
op_helper.c	target-arm: don't generate WFE/YIELD calls for MTTCG	2018-03-02 10:27:36 -05:00
psci.c	target/arm/psci.c: If EL2 implemented, start CPUs in EL2	2018-03-01 23:34:57 -05:00
translate-a64.c	Add missing fp_access_check() to aarch64 crypto instructions	2018-03-02 10:39:16 -05:00
translate.c	target-arm: don't generate WFE/YIELD calls for MTTCG	2018-03-02 10:27:36 -05:00
translate.h	target/arm: A32, T32: Create Instruction Syndromes for Data Aborts	2018-03-02 00:37:06 -05:00
unicorn_aarch64.c
unicorn_arm.c
unicorn.h