Fabien Chouteau 7e6d37b51d RISC-V: fix single stepping over ret and other branching instructions ... This patch introduces wrappers around the tcg_gen_exit_tb() and tcg_gen_lookup_and_goto_ptr() functions that handle single stepping, i.e. call gen_exception_debug() when single stepping is enabled. Theses functions are then used instead of the originals, bringing single stepping handling in places where it was previously ignored such as jalr and system branch instructions (ecall, mret, sret, etc.). Backports commit 6e2716d8ca4edf3597307accef7af36e8ad966eb from qemu		2019-05-28 18:35:07 -04:00
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insn_trans	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 23:39:49 -04:00
cpu_helper.c	tcg: Use CPUClass::tlb_fill in cputlb.c	2019-05-16 17:35:37 -04:00
cpu_user.h	RISC-V: linux-user support for RVE ABI	2019-03-19 23:58:31 -04:00
cpu.c	target/riscv: Convert to CPUClass::tlb_fill	2019-05-16 17:24:01 -04:00
cpu.h	target/riscv: Convert to CPUClass::tlb_fill	2019-05-16 17:24:01 -04:00
csr.c	RISC-V: Add support for vectored interrupts	2019-03-19 23:58:31 -04:00
fpu_helper.c
helper.h
insn16.decode	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-19 04:53:07 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-19 05:17:54 -04:00
instmap.h
Makefile.objs	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
op_helper.c	target/riscv: Do not allow sfence.vma from user mode	2019-05-28 18:29:46 -04:00
pmp.c	riscv: pmp: Log pmp access errors as guest errors	2019-03-19 23:45:03 -04:00
pmp.h	Clean up ill-advised or unusual header guards	2019-05-14 08:02:53 -04:00
translate.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
unicorn.c
unicorn.h