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7e9b84ca1a
unicorn/qemu/target
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James Hogan 7e9b84ca1a
target/mips: Add an MMU mode for ERL 
The segmentation control feature allows a legacy memory segment to
become unmapped uncached at error level (according to CP0_Status.ERL),
and in fact the user segment is already treated in this way by QEMU.

Add a new MMU mode for this state so that QEMU's mappings don't persist
between ERL=0 and ERL=1.

Backports commit 42c86612d507c2a8789f2b8d920a244693c4ef7b from qemu
2018-03-04 00:47:19 -05:00
..
arm tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00
i386 tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00
m68k tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00
mips target/mips: Add an MMU mode for ERL 2018-03-04 00:47:19 -05:00
sparc tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00