unicorn/qemu/target
Marc Zyngier 145d58c367
target/arm: Honor HCR_EL2.TID3 trapping requirements
HCR_EL2.TID3 mandates that access from EL1 to a long list of id
registers traps to EL2, and QEMU has so far ignored this requirement.

This breaks (among other things) KVM guests that have PtrAuth enabled,
while the hypervisor doesn't want to expose the feature to its guest.
To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this
case), and masks out the unsupported feature.

QEMU not honoring the trap request means that the guest observes
that the feature is present in the HW, starts using it, and dies
a horrible death when KVM injects an UNDEF, because the feature
*really* isn't supported.

Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set.

Note that this change does not include trapping of the MVFR
registers from AArch32 (they are accessed via the VMRS
instruction and need to be handled in a different way).

Backports commit 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317 from qemu
2019-11-28 03:46:32 -05:00
..
arm target/arm: Honor HCR_EL2.TID3 trapping requirements 2019-11-28 03:46:32 -05:00
i386 tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
m68k tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
mips tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
riscv tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
sparc tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00