unicorn/qemu/target
Konrad Rzeszutek Wilk 860411e045
i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)
"Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD). To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.

Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present." (from x86/speculation: Add virtualized
speculative store bypass disable support in Linux).

Backports commit cfeea0c021db6234c154dbc723730e81553924ff from qemu
2018-05-22 16:57:39 -04:00
..
arm target/arm: Implement SVE Permute - Extract Group 2018-05-20 05:26:55 -04:00
i386 i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639) 2018-05-22 16:57:39 -04:00
m68k tcg: fix s/compliment/complement/ typos 2018-05-22 00:29:51 -04:00
mips target/mips: Remove floatX_maybe_silence_nan from conversions 2018-05-19 23:25:04 -04:00
sparc target/sparc: convert to TranslatorOps 2018-05-11 15:17:12 -04:00