unicorn/qemu/target
Marc Zyngier 868de52f69 target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.

Tested with a hacked-up version of KVM/arm64 that sets the control
bits for 32bit guests.

Backports commit 9ca1d776cb49c09b09579d9edd0447542970c834 from qemu
2020-01-07 18:04:16 -05:00
..
arm target/arm: Handle trapping to EL2 of AArch32 VMRS instructions 2020-01-07 18:04:16 -05:00
i386 tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
m68k tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
mips tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
riscv tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
sparc tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00