Yongbok Kim 89cc42c8e2 target/mips: Add nanoMIPS base instruction set opcodes ... Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called instruction pools. Each pool contains a set of opcodes, that in turn can be instruction opcodes or instruction pool opcodes. Backports commit 261c95a0e98e5e9b13c9c005a991b7e7dc27f38a from qemu		2018-08-27 04:12:53 -04:00
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arm	target/arm: Remove a handful of stray tabs	2018-08-25 04:34:44 -04:00
i386	target/i386: update MPX flags when CPL changes	2018-08-25 03:32:22 -04:00
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-15 11:40:18 -04:00
mips	target/mips: Add nanoMIPS base instruction set opcodes	2018-08-27 04:12:53 -04:00
sparc	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-07 11:56:32 -04:00