Leon Alrae 8fadc55db3 target-mips: make ITC Configuration Tags accessible to the CPU ... Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv processors these bits are used to enable CACHE instruction access to different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will access ITC tag values. Generally we do not model caches and we have been treating the CACHE instruction as NOP. But since CACHE can operate on ITC Tags new MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when CACHE is in the ITC Access mode. Backports commit 0d74a222c27e26fc40f4f6120c61c3f9ceaa3776 from qemu		2018-03-04 00:34:30 -05:00
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arm	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
i386	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
m68k	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
mips	target-mips: make ITC Configuration Tags accessible to the CPU	2018-03-04 00:34:30 -05:00
sparc	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00