Yongbok Kim 922d30c448 target-mips: Misaligned memory accesses for MSA ... MIPS SIMD Architecture vector loads and stores require misalignment support. MSA Memory access should work as an atomic operation. Therefore, it has to check validity of all addresses for a vector store access if it is spanning into two pages. Separating helper functions for each data format as format is known in translation. To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag. Removing save_cpu_state() call in translation because it is able to use cpu_restore_state() on fault as GETRA() is passed. Backports commit adc370a48fd26b92188fa4848dfb088578b1936c from qemu		2018-02-13 13:27:31 -05:00
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cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	Fix for MIPS issue. (#733)	2017-01-23 12:39:34 +08:00
cpu.h	target-mips: add Config5.FRE support allowing Status.FR=0 emulation	2018-02-13 13:05:22 -05:00
dsp_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
helper.c	target-mips: remove excp_names[] from linux-user as it is unused	2018-02-11 17:05:40 -05:00
helper.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
lmi_helper.c	import	2015-08-21 15:04:50 +08:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	import	2015-08-21 15:04:50 +08:00
msa_helper.c	target-mips: add missing MSACSR and restore fp_status and hflags	2018-02-12 16:12:17 -05:00
op_helper.c	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
TODO	import	2015-08-21 15:04:50 +08:00
translate_init.c	target-mips: add Config5.FRE support allowing Status.FR=0 emulation	2018-02-13 13:05:22 -05:00
translate.c	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
unicorn.c	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00