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9727b7c3e0
unicorn/qemu
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Aaron Lindsay 9727b7c3e0
target/arm: PMU: Set PMCR.N to 4 
This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.

Backports commit ac689a2e5155d129acaa39603e2a7a29abd90d89 from qemu
2019-01-22 18:55:34 -05:00
..
accel tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZE 2018-11-16 21:35:54 -05:00
crypto
default-configs
docs
fpu hardfloat: implement float32/64 comparison 2018-12-19 10:45:22 -05:00
hw
include qemu/compiler: Define QEMU_NONSTRING 2019-01-22 15:06:09 -05:00
qapi qapi: Rewrite string-input-visitor's integer and list parsing 2018-12-18 04:57:25 -05:00
qobject
qom tcg: access cpu->icount_decr.u16.high with atomics 2018-10-23 14:36:46 -04:00
scripts qapi: fix flat union on uncovered branches conditionals 2018-12-19 10:53:29 -05:00
target target/arm: PMU: Set PMCR.N to 4 2019-01-22 18:55:34 -05:00
tcg tcg: Improve call argument loading 2019-01-05 07:24:08 -05:00
util qemu-thread: Don't block SEGV, ILL and FPE 2019-01-13 19:50:32 -05:00
aarch64.h target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 2019-01-22 17:45:36 -05:00
aarch64eb.h target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 2019-01-22 17:45:36 -05:00
accel.c
arm.h target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 2019-01-22 17:45:36 -05:00
armeb.h target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 2019-01-22 17:45:36 -05:00
CODING_STYLE
configure configure: keep track of Python version 2019-01-22 15:07:59 -05:00
COPYING
COPYING.LIB
cpus.c
exec.c Partial backport of: exec.c: Handle IOMMUs in address_space_translate_for_iotlb() 2018-11-16 21:24:55 -05:00
gen_all_header.sh
glib_compat.c
HACKING
header_gen.py target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 2019-01-22 17:45:36 -05:00
ioport.c
LICENSE
m68k.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00
Makefile
Makefile.objs
Makefile.target configure: Remove old -fno-gcse workaround for GCC 4.6.x and 4.7.[012] 2018-12-18 03:52:36 -05:00
memory_ldst.inc.c
memory_mapping.c
memory.c memory: learn about non-volatile memory region 2018-11-11 08:50:39 -05:00
mips64.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00
mips64el.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00
mips.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00
mipsel.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00
powerpc.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00
qemu-timer.c
riscv32.h
riscv64.h
rules.mak
sparc64.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00
sparc.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00
unicorn_common.h
VERSION Open 4.0 development tree 2018-12-11 20:33:45 -05:00
vl.c
vl.h
x86_64.h target/arm: Reorganize PMCCNTR accesses 2019-01-22 16:57:29 -05:00