Richard Henderson 9d2a3064af target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word ... Separate shift + extract low will result in one extra insn for hosts like RISC-V, MIPS, and Sparc. Backports commit 664b7e3b97d6376f3329986c465b3782458b0f8b from qemu		2019-11-18 20:36:19 -05:00
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arm	target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word	2019-11-18 20:36:19 -05:00
i386	x86: setup FS & GS base	2019-08-08 20:26:45 -04:00
m68k	m68k comments break patch submission due to being incorrectly formatted	2019-08-08 14:26:45 -04:00
mips	Removed hardcoded CP0C3_ULRI (#1098)	2019-08-08 20:08:57 -04:00
riscv	RISC-V: Clear load reservations on context switch and SC	2019-08-08 17:15:45 -04:00
sparc	cpu: Introduce CPUNegativeOffsetState	2019-06-13 15:08:25 -04:00