unicorn/qemu/include/hw
Lioncash b6f752970b
target/riscv: Initial introduction of the RISC-V target
This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.
2019-03-08 21:46:10 -05:00
..
arm Use DEFINE_MACHINE() to register all machines 2018-03-11 15:12:46 -04:00
cpu
i386 i386: keep cpu_model field in MachineState uptodate 2018-03-20 12:40:35 -04:00
m68k Use DEFINE_MACHINE() to register all machines 2018-03-11 15:12:46 -04:00
mips Use DEFINE_MACHINE() to register all machines 2018-03-11 15:12:46 -04:00
riscv target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
sparc Revert use of DEFINE_MACHINE() for registrations of multiple machines 2018-03-11 15:17:17 -04:00
xen
boards.h Use cpu_create(type) instead of cpu_init(cpu_model) 2018-03-20 14:20:30 -04:00
hw.h
qdev-core.h bus: simplify name handling 2018-03-09 13:02:15 -05:00
qdev.h
registerfields.h armv7m: Fix reads of CONTROL register bit 1 2018-03-02 13:26:38 -05:00