James Hogan b35fb57c84 target/mips: Enable CP0_EBase.WG on MIPS64 CPUs ... Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic CPUs. This allows 64-bit guests to run KVM itself, which uses CP0_EBase.WG to point CP0_EBase at XKPhys. Backports commit bad63a8008a0aaefcd00542c89bee01623d7c9de from qemu		2018-03-04 01:09:47 -05:00
..
cpu-qom.h
cpu.c
cpu.h	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
dsp_helper.c
helper.c	target/mips: Implement segmentation control	2018-03-04 01:06:13 -05:00
helper.h	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
lmi_helper.c
Makefile.objs
mips-defs.h
msa_helper.c
op_helper.c	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
TODO
translate_init.c	target/mips: Enable CP0_EBase.WG on MIPS64 CPUs	2018-03-04 01:09:47 -05:00
translate.c	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
unicorn.c
unicorn.h