mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-10-21 13:08:20 +02:00
81c14bb595
ARMv8.2 introduced support for Data Cache Clean instructions to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence) - DV CVADP. Both specify conceptual points in a memory system where all writes that are to reach them are considered persistent. The support provided considers both to be actually the same so there is no distinction between the two. If none is available (there is no backing store for given memory) both will result in Data Cache Clean up to the point of coherency. Otherwise sync for the specified range shall be performed. Backports commit 0d57b49992200a926c4436eead97ecfc8cc710be from qemu
432 lines
16 KiB
C
432 lines
16 KiB
C
/*
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* QEMU AArch64 CPU
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*
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* Copyright (c) 2013 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "hw/arm/arm.h"
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#include "sysemu/sysemu.h"
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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static inline QEMU_UNUSED_FUNC void unset_feature(CPUARMState *env, int feature)
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{
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env->features &= ~(1ULL << feature);
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}
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#ifndef CONFIG_USER_ONLY
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static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = env_archcpu(env);
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/* Number of cores is in [25:24]; otherwise we RAZ */
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return (cpu->core_count - 1) << 24;
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}
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#endif
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static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
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#ifndef CONFIG_USER_ONLY
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{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
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.access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
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.writefn = arm_cp_write_ignore },
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{ .name = "L2CTLR",
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.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
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.access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
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.writefn = arm_cp_write_ignore },
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#endif
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{ .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2ECTLR",
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.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR",
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.cp = 15, .opc1 = 0, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUECTLR",
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.cp = 15, .opc1 = 1, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUMERRSR",
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.cp = 15, .opc1 = 2, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2MERRSR",
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.cp = 15, .opc1 = 3, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->midr = 0x411fd070;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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cpu->dtb_compatible = "arm,cortex-a53";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
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cpu->midr = 0x410fd034;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x84448004; /* L1Ip = VIPT */
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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static void aarch64_a72_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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cpu->dtb_compatible = "arm,cortex-a72";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->midr = 0x410fd083;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034080;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
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* otherwise, a CPU with as many features enabled as our emulation supports.
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* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
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* this only needs to handle 64 bits.
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*/
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static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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uint64_t t;
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uint32_t u;
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aarch64_a57_initfn(uc, obj, opaque);
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/*
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* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
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* one and try to apply errata workarounds or use impdef features we
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* don't provide.
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* An IMPLEMENTER field of 0 means "reserved for software use";
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* ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
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* to see which features are present";
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* the VARIANT, PARTNUM and REVISION fields are all implementation
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* defined and we choose to define PARTNUM just in case guest
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* code needs to distinguish this QEMU CPU from other software
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* implementations, though this shouldn't be needed.
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*/
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t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
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t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
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t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
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t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
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t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
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cpu->midr = t;
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t = cpu->isar.id_aa64isar0;
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t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
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t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
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t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
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t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
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cpu->isar.id_aa64isar0 = t;
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t = cpu->isar.id_aa64isar1;
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t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
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t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
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t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
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t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
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t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
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cpu->isar.id_aa64isar1 = t;
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t = cpu->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
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cpu->isar.id_aa64pfr0 = t;
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t = cpu->isar.id_aa64pfr1;
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t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
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cpu->isar.id_aa64pfr1 = t;
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t = cpu->isar.id_aa64mmfr1;
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t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
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t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
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cpu->isar.id_aa64mmfr1 = t;
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/* Replicate the same data to the 32-bit id registers. */
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u = cpu->isar.id_isar5;
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u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
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u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
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u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
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u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
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u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
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u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
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cpu->isar.id_isar5 = u;
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u = cpu->isar.id_isar6;
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u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
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u = FIELD_DP32(u, ID_ISAR6, DP, 1);
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u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
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u = FIELD_DP32(u, ID_ISAR6, SB, 1);
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u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
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cpu->isar.id_isar6 = u;
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// Unicorn: we lie and enable them anyway
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/*
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* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
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* so do not set MVFR1.FPHP. Strictly speaking this is not legal,
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* but it is also not legal to enable SVE without support for FP16,
|
|
* and enabling SVE in system mode is more useful in the short term.
|
|
*/
|
|
/* For usermode -cpu max we can use a larger and more efficient DCZ
|
|
* blocksize since we don't have to follow what the hardware does.
|
|
*/
|
|
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
|
|
cpu->dcz_blocksize = 7; /* 512 bytes */
|
|
|
|
/* Enable all PAC keys by default. */
|
|
cpu->env.cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB;
|
|
cpu->env.cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB;
|
|
|
|
cpu->sve_max_vq = ARM_MAX_VQ;
|
|
}
|
|
|
|
typedef struct ARMCPUInfo {
|
|
const char *name;
|
|
void (*initfn)(struct uc_struct *uc, Object *obj, void *opaque);
|
|
void (*class_init)(struct uc_struct *uc, ObjectClass *oc, void *data);
|
|
} ARMCPUInfo;
|
|
|
|
static const ARMCPUInfo aarch64_cpus[] = {
|
|
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
|
|
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
|
|
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
|
|
{ .name = "max", .initfn = aarch64_max_initfn },
|
|
{ .name = NULL }
|
|
};
|
|
|
|
static QEMU_UNUSED_FUNC bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(NULL, obj);
|
|
|
|
return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
}
|
|
|
|
static void aarch64_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
|
|
{
|
|
}
|
|
|
|
static void aarch64_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaque)
|
|
{
|
|
}
|
|
|
|
static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
|
|
{
|
|
CPUClass *cc = CPU_CLASS(uc, oc);
|
|
|
|
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
|
|
}
|
|
|
|
static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
|
|
{
|
|
TypeInfo type_info = {
|
|
.parent = TYPE_AARCH64_CPU,
|
|
.instance_size = sizeof(ARMCPU),
|
|
.instance_init = info->initfn,
|
|
.class_size = sizeof(ARMCPUClass),
|
|
.class_init = info->class_init,
|
|
.class_data = (void *)info,
|
|
};
|
|
|
|
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
|
type_register(uc, &type_info);
|
|
g_free((void *)type_info.name);
|
|
}
|
|
|
|
void aarch64_cpu_register_types(void *opaque)
|
|
{
|
|
const ARMCPUInfo *info = aarch64_cpus;
|
|
|
|
static TypeInfo aarch64_cpu_type_info = { 0 };
|
|
aarch64_cpu_type_info.name = TYPE_AARCH64_CPU;
|
|
aarch64_cpu_type_info.parent = TYPE_ARM_CPU;
|
|
aarch64_cpu_type_info.instance_size = sizeof(ARMCPU);
|
|
aarch64_cpu_type_info.instance_init = aarch64_cpu_initfn;
|
|
aarch64_cpu_type_info.instance_finalize = aarch64_cpu_finalizefn;
|
|
aarch64_cpu_type_info.abstract = true;
|
|
aarch64_cpu_type_info.class_size = sizeof(AArch64CPUClass);
|
|
aarch64_cpu_type_info.class_init = aarch64_cpu_class_init;
|
|
|
|
type_register_static(opaque, &aarch64_cpu_type_info);
|
|
|
|
while (info->name) {
|
|
aarch64_cpu_register(opaque, info);
|
|
info++;
|
|
}
|
|
}
|