Richard Henderson c4b2493c2e target/arm: Improve masking of HCR/HCR2 RES0 bits ... Don't merely start with v8.0, handle v7VE as well. Ensure that writes from aarch32 mode do not change bits in the other half of the register. Protect reads of aa64 id registers with ARM_FEATURE_AARCH64. Backports commit d1fb4da208411ce7b3dafb9f9e7726ebcec14edb from qemu		2020-03-22 02:28:41 -04:00
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arm	target/arm: Improve masking of HCR/HCR2 RES0 bits	2020-03-22 02:28:41 -04:00
i386	target/i386: check for empty register in FXAM	2020-03-21 19:43:24 -04:00
m68k	m68k: Fix regression causing Single-Step via GDB/RSP to not single step	2020-03-21 12:15:08 -04:00
mips	target/arm: fix TCG leak for fcvt half->double	2020-03-21 13:14:47 -04:00
riscv	target/riscv: Emulate TIME CSRs for privileged mode	2020-03-22 02:22:17 -04:00
sparc	target/sparc: sun4u Invert Endian TTE bit	2020-01-07 19:21:30 -05:00