unicorn/qemu
Peter Maydell cdb9422f3a
target/arm: NS BusFault on vector table fetch escalates to NS HardFault
In the M-profile architecture, when we do a vector table fetch and it
fails, we need to report a HardFault. Whether this is a Secure HF or
a NonSecure HF depends on several things. If AIRCR.BFHFNMINS is 0
then HF is always Secure, because there is no NonSecure HardFault.
Otherwise, the answer depends on whether the 'underlying exception'
(MemManage, BusFault, SecureFault) targets Secure or NonSecure. (In
the pseudocode, this is handled in the Vector() function: the final
exc.isSecure is calculated by looking at the exc.isSecure from the
exception returned from the memory access, not the isSecure input
argument.)

We weren't doing this correctly, because we were looking at
the target security domain of the exception we were trying to
load the vector table entry for. This produces errors of two kinds:
* a load from the NS vector table which hits the "NS access
to S memory" SecureFault should end up as a Secure HardFault,
but we were raising an NS HardFault
* a load from the S vector table which causes a BusFault
should raise an NS HardFault if BFHFNMINS == 1 (because
in that case all BusFaults are NonSecure), but we were raising
a Secure HardFault

Correct the logic.

We also fix a comment error where we claimed that we might
be escalating MemManage to HardFault, and forgot about SecureFault.
(Vector loads can never hit MPU access faults, because they're
always aligned and always use the default address map.)

Backports commit 51c9122e92b776a3f16af0b9282f1dc5012e2a19 from qemu
2019-08-08 19:32:53 -04:00
..
accel Revert "cputlb: Filter flushes on already clean tlbs" 2019-06-30 19:21:20 -04:00
crypto
default-configs target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
docs
fpu qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
hw i386: Update new x86_apicid parsing rules with die_offset support 2019-08-08 18:22:03 -04:00
include include/qemu/atomic.h: Add signal_barrier 2019-08-08 19:26:41 -04:00
qapi
qobject
qom cpu: Move icount_decr to CPUNegativeOffsetState 2019-06-13 15:34:28 -04:00
scripts decodetree: Fix comparison of Field 2019-06-13 16:17:56 -04:00
target target/arm: NS BusFault on vector table fetch escalates to NS HardFault 2019-08-08 19:32:53 -04:00
tcg tcg/aarch64: Fix output of extract2 opcodes 2019-08-08 19:25:37 -04:00
util util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64 2019-05-09 17:43:27 -04:00
aarch64.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
aarch64eb.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
accel.c
arm.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
armeb.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
CODING_STYLE
configure Deprecate Python 2 support 2019-08-08 17:16:26 -04:00
COPYING
COPYING.LIB
cpus.c
exec.c exec.c: refactor function flatview_add_to_dispatch() 2019-03-11 17:00:46 -04:00
gen_all_header.sh
glib_compat.c target/arm/translate: Synchronize with Qemu 2019-04-27 10:13:01 -04:00
HACKING
header_gen.py target/riscv: Implement riscv_cpu_unassigned_access 2019-08-08 16:48:02 -04:00
ioport.c
LICENSE
m68k.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00
Makefile Makefile: Rename targets for make recursion 2019-08-08 17:26:49 -04:00
Makefile.objs
Makefile.target
memory_ldst.inc.c
memory_mapping.c
memory.c cputlb: Synchronize with qemu 2019-04-26 15:48:45 -04:00
mips64.h target/mips: Refactor and fix INSERT.<B|H|W|D> instructions 2019-05-28 19:42:28 -04:00
mips64el.h target/mips: Refactor and fix INSERT.<B|H|W|D> instructions 2019-05-28 19:42:28 -04:00
mips.h target/mips: Refactor and fix INSERT.<B|H|W|D> instructions 2019-05-28 19:42:28 -04:00
mipsel.h target/mips: Refactor and fix INSERT.<B|H|W|D> instructions 2019-05-28 19:42:28 -04:00
powerpc.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00
qemu-timer.c
riscv32.h target/riscv: Implement riscv_cpu_unassigned_access 2019-08-08 16:48:02 -04:00
riscv64.h target/riscv: Implement riscv_cpu_unassigned_access 2019-08-08 16:48:02 -04:00
rules.mak
sparc64.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00
sparc.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00
unicorn_common.h
VERSION Update version for v4.1.0-rc0 release 2019-08-08 19:23:58 -04:00
vl.c
vl.h
x86_64.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00