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unicorn/qemu/target/riscv/insn_trans
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Alistair Francis 1e17cbc52c target/riscv: Remove the hret instruction 
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.

Backports commit 0736febb2d0e1bb503ca07091c16a16e78480366 from qemu
2020-03-22 01:44:55 -04:00
..
trans_privileged.inc.c target/riscv: Remove the hret instruction 2020-03-22 01:44:55 -04:00
trans_rva.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvd.inc.c target/riscv: fsd/fsw doesn't dirty FP state 2020-03-21 12:20:52 -04:00
trans_rvf.inc.c target/riscv: fsd/fsw doesn't dirty FP state 2020-03-21 12:20:52 -04:00
trans_rvi.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvm.inc.c target/riscv: Zero extend the inputs of divuw and remuw 2019-03-26 20:38:17 -04:00