Mateja Marjanovic d712d3f226 target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware ... MSA instructions DIV_<U|S>.<B|H|W|D> when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 141, 142). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Backports commit d2a40a5f6938f30f44b536e997e1e89bb62b971c from qemu		2019-05-28 19:24:26 -04:00
..
cp0_timer.c
cpu-qom.h
cpu.c	target/mips: Convert to CPUClass::tlb_fill	2019-05-16 17:19:47 -04:00
cpu.h	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
dsp_helper.c
helper.c	tcg: Use CPUClass::tlb_fill in cputlb.c	2019-05-16 17:35:37 -04:00
helper.h	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
internal.h	target/mips: Convert to CPUClass::tlb_fill	2019-05-16 17:19:47 -04:00
lmi_helper.c
Makefile.objs
mips-defs.h	target/mips: Define a bit for MXU in insn_flags	2018-11-11 05:52:18 -05:00
msa_helper.c	target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware	2019-05-28 19:24:26 -04:00
op_helper.c	target/mips: Convert to CPUClass::tlb_fill	2019-05-16 17:19:47 -04:00
TODO
translate_init.c	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
translate.c	tcg: Hoist max_insns computation to tb_gen_code	2019-04-30 09:49:57 -04:00
unicorn.c
unicorn.h