unicorn/qemu/target
Peter Maydell d89704eb0f
target/i386: Fix handling of VEX prefixes
In commit e3af7c788b73a6495eb9d94992ef11f6ad6f3c56 we
replaced direct calls to to cpu_ld*_code() with calls
to the x86_ld*_code() wrappers which incorporate an
advance of s->pc. Unfortunately we didn't notice that
in one place the old code was deliberately not incrementing
s->pc:

@@ -4501,7 +4528,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
static const int pp_prefix[4] = {
0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
};
- int vex3, vex2 = cpu_ldub_code(env, s->pc);
+ int vex3, vex2 = x86_ldub_code(env, s);

if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
/* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,

This meant we were mishandling this set of instructions.
Remove the manual advance of s->pc for the "is VEX" case
(which is now done by x86_ldub_code()) and instead rewind
PC in the case where we decide that this isn't really VEX.

Backports commit 817a9fcba8043faa467929e7b0193df6bdc92211 from qemu
2018-03-05 13:48:29 -05:00
..
arm target/arm: Generate UNDEF for 32-bit Thumb2 insns 2018-03-05 13:48:29 -05:00
i386 target/i386: Fix handling of VEX prefixes 2018-03-05 13:48:29 -05:00
m68k qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
mips qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
sparc qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00