Peter Maydell 6b413ffa97 target/i386: Generate #UD for LOCK on a register increment ... Fix a TCG crash due to attempting an atomic increment operation without having set up the address first. This is a similar case to that dealt with in commit e84fcd7f662a0d8198703, and we fix it in the same way. Fixes: https://bugs.launchpad.net/qemu/+bug/1807675 Backports commit 8cb2ca3d7479748587313f0b34034a3f8aa08c92 from qemu		2019-04-09 09:28:46 -04:00
..
arch_memory_mapping.c
bpt_helper.c	target/i386/bpt_helper: Perform comparison pass with qemu	2018-03-12 13:28:50 -04:00
cc_helper_template.h
cc_helper.c
cpu-qom.h
cpu.c	i386: Disable OSPKE on CPU model definitions	2019-03-22 09:46:44 -04:00
cpu.h	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:40:23 -04:00
excp_helper.c	target/i386: rename HF_SVMI_MASK to HF_GUEST_MASK	2018-10-04 04:24:39 -04:00
fpu_helper.c
helper.c	icount: fix cpu_restore_state_from_tb for non-tb-exit cases	2018-04-11 20:05:40 -04:00
helper.h
int_helper.c
Makefile.objs
mem_helper.c	target/i386: Convert to HAVE_CMPXCHG128	2018-10-23 15:21:03 -04:00
misc_helper.c	i386: implement MSR_SMI_COUNT for TCG	2018-08-02 21:27:08 -04:00
mpx_helper.c
ops_sse_header.h
ops_sse.h
seg_helper.c	target/i386: Clear RF on SYSCALL instruction	2018-11-11 08:41:09 -05:00
shift_helper_template.h
smm_helper.c	i386: implement MSR_SMI_COUNT for TCG	2018-08-02 21:27:08 -04:00
svm_helper.c	target/i386: rename HF_SVMI_MASK to HF_GUEST_MASK	2018-10-04 04:24:39 -04:00
svm.h	target-i386: Add NPT support	2018-07-03 19:52:56 -04:00
TODO
topology.h
translate.c	target/i386: Generate #UD for LOCK on a register increment	2019-04-09 09:28:46 -04:00
unicorn.c	[Fix] Add feature support for CMPXCHG16B instruction. (#983)	2019-02-28 17:03:08 -05:00
unicorn.h