David Hildenbrand de513617c8 accel/tcg: allow to invalidate a write TLB entry immediately ... Background: s390x implements Low-Address Protection (LAP). If LAP is enabled, writing to effective addresses (before any translation) 0-511 and 4096-4607 triggers a protection exception. So we have subpage protection on the first two pages of every address space (where the lowcore - the CPU private data resides). By immediately invalidating the write entry but allowing the caller to continue, we force every write access onto these first two pages into the slow path. we will get a tlb fault with the specific accessed addresses and can then evaluate if protection applies or not. We have to make sure to ignore the invalid bit if tlb_fill() succeeds. Backports commit f52bfb12143e29d7c8bd827bdb751aee47a9694e from qemu		2020-01-14 07:14:10 -05:00
..
atomic_template.h	atomic_template: fix indentation in GEN_ATOMIC_HELPER	2019-11-28 02:38:07 -05:00
cpu-exec-common.c	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
cpu-exec.c	cpu: Move icount_decr to CPUNegativeOffsetState	2019-06-13 15:34:28 -04:00
cputlb.c	accel/tcg: allow to invalidate a write TLB entry immediately	2020-01-14 07:14:10 -05:00
Makefile.objs
tcg-runtime-gvec.c	tcg: Fix typos in helper_gvec_sar{8,32,64}v	2019-06-13 16:09:16 -04:00
tcg-runtime.c	cpu: Replace ENV_GET_CPU with env_cpu	2019-06-12 11:16:16 -04:00
tcg-runtime.h	tcg: Add support for vector bitwise select	2019-05-24 18:15:10 -04:00
translate-all.c	cpu: Move icount_decr to CPUNegativeOffsetState	2019-06-13 15:34:28 -04:00
translate-all.h	tcg: Synchronize with qemu	2019-04-26 09:32:20 -04:00
translate-common.c	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
translator.c	tcg: Hoist max_insns computation to tb_gen_code	2019-04-30 09:49:57 -04:00