mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-10-19 18:48:19 +02:00
064543a415
Allow qemu to build on 32-bit hosts without 64-bit atomic ops. Even if we only allow 32-bit hosts to multi-thread emulate 32-bit guests, we still need some way to handle the 32-bit guest using a 64-bit atomic operation. Do so by dropping back to single-step. Backports commit df79b996a7b21c6ea7847f7927a2e1a294b86c72 from qemu
127 lines
5.9 KiB
C
127 lines
5.9 KiB
C
DEF_HELPER_FLAGS_2(div_i32, TCG_CALL_NO_RWG_SE, s32, s32, s32)
|
|
DEF_HELPER_FLAGS_2(rem_i32, TCG_CALL_NO_RWG_SE, s32, s32, s32)
|
|
DEF_HELPER_FLAGS_2(divu_i32, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
|
DEF_HELPER_FLAGS_2(remu_i32, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
|
|
|
DEF_HELPER_FLAGS_2(div_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
|
|
DEF_HELPER_FLAGS_2(rem_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
|
|
DEF_HELPER_FLAGS_2(divu_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
|
DEF_HELPER_FLAGS_2(remu_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
|
|
|
DEF_HELPER_FLAGS_2(shl_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
|
DEF_HELPER_FLAGS_2(shr_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
|
DEF_HELPER_FLAGS_2(sar_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
|
|
|
|
DEF_HELPER_FLAGS_2(mulsh_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
|
|
DEF_HELPER_FLAGS_2(muluh_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
|
|
|
DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env)
|
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
|
|
DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG,
|
|
i32, env, tl, i32, i32, i32)
|
|
DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG,
|
|
i32, env, tl, i32, i32, i32)
|
|
DEF_HELPER_FLAGS_5(atomic_cmpxchgw_le, TCG_CALL_NO_WG,
|
|
i32, env, tl, i32, i32, i32)
|
|
DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG,
|
|
i32, env, tl, i32, i32, i32)
|
|
DEF_HELPER_FLAGS_5(atomic_cmpxchgl_le, TCG_CALL_NO_WG,
|
|
i32, env, tl, i32, i32, i32)
|
|
|
|
#ifdef CONFIG_ATOMIC64
|
|
DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG,
|
|
i64, env, tl, i64, i64, i32)
|
|
DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG,
|
|
i64, env, tl, i64, i64, i32)
|
|
#endif
|
|
|
|
#ifdef CONFIG_ATOMIC64
|
|
#define GEN_ATOMIC_HELPERS(NAME) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_le), \
|
|
TCG_CALL_NO_WG, i64, env, tl, i64, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_be), \
|
|
TCG_CALL_NO_WG, i64, env, tl, i64, i32)
|
|
#else
|
|
#define GEN_ATOMIC_HELPERS(NAME) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
|
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
|
#endif /* CONFIG_ATOMIC64 */
|
|
|
|
#else
|
|
|
|
DEF_HELPER_FLAGS_4(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
|
DEF_HELPER_FLAGS_4(atomic_cmpxchgw_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
|
DEF_HELPER_FLAGS_4(atomic_cmpxchgw_le, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
|
DEF_HELPER_FLAGS_4(atomic_cmpxchgl_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
|
DEF_HELPER_FLAGS_4(atomic_cmpxchgl_le, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
|
#ifdef CONFIG_ATOMIC64
|
|
DEF_HELPER_FLAGS_4(atomic_cmpxchgq_be, TCG_CALL_NO_WG, i64, env, tl, i64, i64)
|
|
DEF_HELPER_FLAGS_4(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64)
|
|
#endif
|
|
|
|
#ifdef CONFIG_ATOMIC64
|
|
#define GEN_ATOMIC_HELPERS(NAME) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_le), \
|
|
TCG_CALL_NO_WG, i64, env, tl, i64) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_be), \
|
|
TCG_CALL_NO_WG, i64, env, tl, i64)
|
|
#else
|
|
#define GEN_ATOMIC_HELPERS(NAME) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
|
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), \
|
|
TCG_CALL_NO_WG, i32, env, tl, i32)
|
|
#endif /* CONFIG_ATOMIC64 */
|
|
|
|
#endif /* CONFIG_SOFTMMU */
|
|
|
|
GEN_ATOMIC_HELPERS(fetch_add)
|
|
GEN_ATOMIC_HELPERS(fetch_and)
|
|
GEN_ATOMIC_HELPERS(fetch_or)
|
|
GEN_ATOMIC_HELPERS(fetch_xor)
|
|
|
|
GEN_ATOMIC_HELPERS(add_fetch)
|
|
GEN_ATOMIC_HELPERS(and_fetch)
|
|
GEN_ATOMIC_HELPERS(or_fetch)
|
|
GEN_ATOMIC_HELPERS(xor_fetch)
|
|
|
|
GEN_ATOMIC_HELPERS(xchg)
|
|
|
|
#undef GEN_ATOMIC_HELPERS
|