Luc MICHEL 393019de26 target/arm: add data cache invalidation cp15 instruction to cortex-r5 ... The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the data cache on the cortex-r5. Implementing it as a NOP. Backports commit 95e9a242e2a393c7d4e5cc04340e39c3a9420f03 from qemu		2018-03-02 20:04:20 -05:00
..
arm	target/arm: add data cache invalidation cp15 instruction to cortex-r5	2018-03-02 20:04:20 -05:00
i386	i386: Don't override -cpu options on -cpu host/max	2018-03-02 14:22:45 -05:00
m68k	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
mips	target/mips: fix delay slot detection in gen_msa_branch()	2018-03-02 14:15:50 -05:00
sparc	cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap	2018-03-02 10:12:40 -05:00