Eduardo Habkost e5e5c2fd6c i386: Register versioned CPU models ... Add support for registration of multiple versions of CPU models. The existing CPU models will be registered with a "-v1" suffix. The -noTSX, -IBRS, and -IBPB CPU model variants will become versions of the original models in a separate patch, so make sure we register no versions for them. Backports commit dcafd1ef0af227ef87f7a6dec8fc66d7d2e2442d from qemu		2019-08-08 19:01:35 -04:00
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arm	target/arm: Correct VMOV_imm_dp handling of short vectors	2019-08-08 18:08:55 -04:00
i386	i386: Register versioned CPU models	2019-08-08 19:01:35 -04:00
m68k	m68k comments break patch submission due to being incorrectly formatted	2019-08-08 14:26:45 -04:00
mips	target/mips: Correct helper for MSA FCLASS.<W|D> instructions	2019-08-08 16:30:15 -04:00
riscv	RISC-V: Clear load reservations on context switch and SC	2019-08-08 17:15:45 -04:00
sparc	cpu: Introduce CPUNegativeOffsetState	2019-06-13 15:08:25 -04:00