Yongbok Kim 46284f1a41 target-mips: implement R6 multi-threading ... MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virtual Processor) bit which indicates presence of multi-threading support which includes CP0.GlobalNumber register and DVP/EVP instructions. Backports commit 01bc435b44b8802cc4697faa07d908684afbce4e from qemu		2018-02-20 22:02:40 -05:00
..
cpu-qom.h
cpu.c	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
cpu.h	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
dsp_helper.c	mips: Clean up includes	2018-02-19 00:45:08 -05:00
helper.c	mips: Clean up includes	2018-02-19 00:45:08 -05:00
helper.h	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
lmi_helper.c	mips: Clean up includes	2018-02-19 00:45:08 -05:00
Makefile.objs
mips-defs.h
msa_helper.c	mips: Clean up includes	2018-02-19 00:45:08 -05:00
op_helper.c	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
TODO
translate_init.c	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
translate.c	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
unicorn.c
unicorn.h