unicorn/qemu/target
Peter Maydell f0c9e690fb
target/arm: Implement HCR.DC
The HCR.DC virtualization configuration register bit has the
following effects:
* SCTLR.M behaves as if it is 0 for all purposes except
direct reads of the bit
* HCR.VM behaves as if it is 1 for all purposes except
direct reads of the bit
* the memory type produced by the first stage of the EL1&EL0
translation regime is Normal Non-Shareable,
Inner Write-Back Read-Allocate Write-Allocate,
Outer Write-Back Read-Allocate Write-Allocate.

Implement this behaviour.

Backports commit 9d1bab337caf2324a233e5937f415fad4ce1641b from qemu
2018-11-10 09:19:44 -05:00
..
arm target/arm: Implement HCR.DC 2018-11-10 09:19:44 -05:00
i386 target/i386: Convert to HAVE_CMPXCHG128 2018-10-23 15:21:03 -04:00
m68k Removes accessible assert 2018-10-06 05:02:20 -04:00
mips target/mips: Add opcodes for nanoMIPS EVA instructions 2018-10-23 14:33:08 -04:00
sparc Sparc increase ttl number 2018-10-06 04:55:52 -04:00