Richard Henderson f175e89ca2 target/mips: Pass a valid error to raise_mmu_exception for user-only ... At present we give ret = 0, or TLBRET_MATCH. This gets matched by the default case, which falls through to TLBRET_BADADDR. However, it makes more sense to use a proper value. All of the tlb-related exceptions are handled identically in cpu_loop.c, so TLBRET_BADADDR is as good as any other. Retain it. Backports commit 995ffde9622c01f5b307cab47f9bd7962ac09db2 from qemu		2019-05-16 17:14:02 -04:00
..
cp0_timer.c
cpu-qom.h	mips: MIPSCPU model subclasses	2018-03-05 00:42:29 -05:00
cpu.c	target/mips/cpu: Use type_register instead of type_register_static() in mips_cpu_register_types()	2018-09-03 17:36:23 -04:00
cpu.h	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
dsp_helper.c
helper.c	target/mips: Pass a valid error to raise_mmu_exception for user-only	2019-05-16 17:14:02 -04:00
helper.h	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
internal.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
lmi_helper.c
Makefile.objs
mips-defs.h	target/mips: Define a bit for MXU in insn_flags	2018-11-11 05:52:18 -05:00
msa_helper.c
op_helper.c	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
TODO
translate_init.c	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
translate.c	tcg: Hoist max_insns computation to tb_gen_code	2019-04-30 09:49:57 -04:00
unicorn.c
unicorn.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00