unicorn/qemu
Palmer Dabbelt fc662c281a
target/riscv: Zero extend the inputs of divuw and remuw
While running the GCC test suite against 4.0.0-rc0, Kito found a
regression introduced by the decodetree conversion that caused divuw and
remuw to sign-extend their inputs. The ISA manual says they are
supposed to be zero extended:

DIVW and DIVUW instructions are only valid for RV64, and divide the
lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as
signed and unsigned integers respectively, placing the 32-bit
quotient in rd, sign-extended to 64 bits. REMW and REMUW
instructions are only valid for RV64, and provide the corresponding
signed and unsigned remainder operations respectively. Both REMW
and REMUW always sign-extend the 32-bit result to 64 bits, including
on a divide by zero.

Here's Kito's reduced test case from the GCC test suite

unsigned calc_mp(unsigned mod)
{
unsigned a,b,c;
c=-1;
a=c/mod;
b=0-a*mod;
if (b > mod) { a += 1; b-=mod; }
return b;
}

int main(int argc, char *argv[])
{
unsigned x = 1234;
unsigned y = calc_mp(x);

if ((sizeof (y) == 4 && y != 680)
|| (sizeof (y) == 2 && y != 134))
abort ();
exit (0);
}

I haven't done any other testing on this, but it does fix the test case.

Backports commit f17e02cd3731bdfe2942d1d0b2a92f26da02408c from qemu
2019-03-26 20:38:17 -04:00
..
accel cputlb: update TLB entry/index after tlb_fill 2019-02-12 11:48:48 -05:00
crypto
default-configs target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
docs
fpu qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
hw target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
include qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
qapi
qobject
qom qom/cpu: Add cluster_index to CPUState 2019-01-30 12:59:59 -05:00
scripts decodetree: Properly diagnose fields overflowing an insn 2019-03-13 11:21:04 -04:00
target target/riscv: Zero extend the inputs of divuw and remuw 2019-03-26 20:38:17 -04:00
tcg target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
util mmap-alloc: fix hugetlbfs misaligned length in ppc64 2019-02-05 16:52:39 -05:00
aarch64.h target/arm: make pmccntr_op_start/finish static 2019-03-26 20:35:34 -04:00
aarch64eb.h target/arm: make pmccntr_op_start/finish static 2019-03-26 20:35:34 -04:00
accel.c
arm.h target/arm: make pmccntr_op_start/finish static 2019-03-26 20:35:34 -04:00
armeb.h target/arm: make pmccntr_op_start/finish static 2019-03-26 20:35:34 -04:00
CODING_STYLE
configure configure: Disable W^X on OpenBSD 2019-03-11 16:46:52 -04:00
COPYING
COPYING.LIB
cpus.c
exec.c exec.c: refactor function flatview_add_to_dispatch() 2019-03-11 17:00:46 -04:00
gen_all_header.sh
glib_compat.c target/arm: expose remaining CPUID registers as RAZ 2019-02-15 17:48:37 -05:00
HACKING
header_gen.py target/arm: make pmccntr_op_start/finish static 2019-03-26 20:35:34 -04:00
ioport.c
LICENSE
m68k.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
Makefile Revert "Makefile: Rename TARGET_DIRS to TARGET_LIST" 2018-07-05 17:40:24 -04:00
Makefile.objs
Makefile.target
memory_ldst.inc.c
memory_mapping.c include/qemu/osdep.h: Don't include qapi/error.h 2018-02-21 23:08:18 -05:00
memory.c
mips64.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
mips64el.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
mips.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
mipsel.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
powerpc.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
qemu-timer.c
riscv32.h RISC-V: Allow interrupt controllers to claim interrupts 2019-03-19 23:48:12 -04:00
riscv64.h RISC-V: Allow interrupt controllers to claim interrupts 2019-03-19 23:48:12 -04:00
rules.mak
sparc64.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
sparc.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
unicorn_common.h
VERSION Update version for v4.0.0-rc0 release 2019-03-19 23:58:31 -04:00
vl.c
vl.h
x86_64.h qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00