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84d5a60c15
ATS1HR and ATS1HW (which allow AArch32 EL2 to do address translations on the EL2 translation regime) were implemented in commit 14db7fe09a2c8. However, we got them wrong: these should do stage 1 address translations as defined for NS-EL2, which is ARMMMUIdx_S1E2. We were incorrectly making them perform stage 2 translations. A few years later in commit 1313e2d7e2cd we forgot entirely that we'd implemented ATS1Hx, and added a comment that ATS1Hx were "not supported yet". Remove the comment; there is no extra code needed to handle these operations in do_ats_write(), because arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2, which forces 64-bit PAR format. Backports commit 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512 from qemu |
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| .. | ||
| arm_ldst.h | ||
| arm-powerctl.c | ||
| arm-powerctl.h | ||
| cpu64.c | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| crypto_helper.c | ||
| helper-a64.c | ||
| helper-a64.h | ||
| helper-sve.h | ||
| helper.c | ||
| helper.h | ||
| internals.h | ||
| iwmmxt_helper.c | ||
| kvm-consts.h | ||
| Makefile.objs | ||
| neon_helper.c | ||
| op_addsub.h | ||
| op_helper.c | ||
| psci.c | ||
| sve_helper.c | ||
| sve.decode | ||
| translate-a64.c | ||
| translate-a64.h | ||
| translate-sve.c | ||
| translate.c | ||
| translate.h | ||
| unicorn_aarch64.c | ||
| unicorn_arm.c | ||
| unicorn.h | ||
| vec_helper.c | ||