Richard Henderson c54b2776f6 tcg: Specify optional vector requirements with a list ... Replace the single opcode in .opc with a null-terminated array in .opt_opc. We still require that all opcodes be used with the same .vece. Validate the contents of this list with CONFIG_DEBUG_TCG. All tcg_gen_*_vec functions will check any list active during .fniv expansion. Swap the active list in and out as we expand other opcodes, or take control away from the front-end function. Convert all existing vector aware front ends. Backports commit 53229a7703eeb2bbe101a19a33ef22aaf960c65b from qemu		2019-05-16 15:05:02 -04:00
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arm	tcg: Specify optional vector requirements with a list	2019-05-16 15:05:02 -04:00
i386	target/i386: check CF_PARALLEL instead of parallel_cpus	2019-05-04 22:45:49 -04:00
m68k	target/m68k: check CF_PARALLEL instead of parallel_cpus	2019-05-06 00:42:16 -04:00
mips	tcg: Hoist max_insns computation to tb_gen_code	2019-04-30 09:49:57 -04:00
riscv	Clean up ill-advised or unusual header guards	2019-05-14 08:02:53 -04:00
sparc	Clean up ill-advised or unusual header guards	2019-05-14 08:02:53 -04:00