2022-04-23 10:59:50 +02:00
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// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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2018-02-12 03:34:20 +01:00
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2018-10-26 05:42:39 +02:00
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#include <cstring>
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2019-11-28 06:15:34 +01:00
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#include <optional>
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2018-02-12 18:34:41 +01:00
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#include "common/assert.h"
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2018-03-25 06:35:06 +02:00
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#include "core/core.h"
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2018-09-01 05:25:18 +02:00
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#include "core/core_timing.h"
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2022-03-11 14:47:01 +01:00
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#include "video_core/dirty_flags.h"
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2022-12-06 06:45:26 +01:00
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#include "video_core/engines/draw_manager.h"
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2018-02-12 03:34:20 +01:00
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#include "video_core/engines/maxwell_3d.h"
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2020-02-10 15:32:51 +01:00
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#include "video_core/gpu.h"
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2019-04-06 00:21:15 +02:00
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#include "video_core/memory_manager.h"
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2018-03-24 07:41:16 +01:00
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#include "video_core/rasterizer_interface.h"
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2018-03-20 00:00:29 +01:00
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#include "video_core/textures/texture.h"
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2018-02-12 03:34:20 +01:00
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2018-10-20 21:58:06 +02:00
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namespace Tegra::Engines {
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2018-02-12 03:34:20 +01:00
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2019-11-28 06:15:34 +01:00
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using VideoCore::QueryType;
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2018-03-18 09:13:22 +01:00
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/// First register id that is actually a Macro call.
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constexpr u32 MacroRegistersStart = 0xE00;
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2020-06-11 05:58:57 +02:00
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Maxwell3D::Maxwell3D(Core::System& system_, MemoryManager& memory_manager_)
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2022-12-06 06:45:26 +01:00
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: draw_manager{std::make_unique<DrawManager>(this)}, system{system_},
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memory_manager{memory_manager_}, macro_engine{GetMacroEngine(*this)}, upload_state{
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memory_manager,
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regs.upload} {
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2019-12-27 02:14:10 +01:00
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dirty.flags.flip();
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2018-10-26 05:42:39 +02:00
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InitializeRegisterDefaults();
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}
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2020-06-11 05:58:57 +02:00
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Maxwell3D::~Maxwell3D() = default;
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2021-01-05 08:09:39 +01:00
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void Maxwell3D::BindRasterizer(VideoCore::RasterizerInterface* rasterizer_) {
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rasterizer = rasterizer_;
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2022-01-29 22:00:49 +01:00
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upload_state.BindRasterizer(rasterizer_);
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2020-06-11 05:58:57 +02:00
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}
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2018-10-26 05:42:39 +02:00
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void Maxwell3D::InitializeRegisterDefaults() {
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// Initializes registers to their default values - what games expect them to be at boot. This is
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// for certain registers that may not be explicitly set by games.
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// Reset all registers to zero
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std::memset(®s, 0, sizeof(regs));
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// Depth range near/far is not always set, but is expected to be the default 0.0f, 1.0f. This is
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// needed for ARMS.
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2019-05-14 14:53:16 +02:00
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for (auto& viewport : regs.viewports) {
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viewport.depth_range_near = 0.0f;
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viewport.depth_range_far = 1.0f;
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2018-10-26 05:42:39 +02:00
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}
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2020-05-04 22:49:48 +02:00
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for (auto& viewport : regs.viewport_transform) {
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viewport.swizzle.x.Assign(Regs::ViewportSwizzle::PositiveX);
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viewport.swizzle.y.Assign(Regs::ViewportSwizzle::PositiveY);
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viewport.swizzle.z.Assign(Regs::ViewportSwizzle::PositiveZ);
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viewport.swizzle.w.Assign(Regs::ViewportSwizzle::PositiveW);
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}
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2019-01-22 08:14:29 +01:00
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2018-11-02 04:21:25 +01:00
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// Doom and Bomberman seems to use the uninitialized registers and just enable blend
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// so initialize blend registers with sane values
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2022-08-12 11:58:09 +02:00
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regs.blend.color_op = Regs::Blend::Equation::Add_D3D;
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regs.blend.color_source = Regs::Blend::Factor::One_D3D;
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regs.blend.color_dest = Regs::Blend::Factor::Zero_D3D;
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regs.blend.alpha_op = Regs::Blend::Equation::Add_D3D;
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regs.blend.alpha_source = Regs::Blend::Factor::One_D3D;
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regs.blend.alpha_dest = Regs::Blend::Factor::Zero_D3D;
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for (auto& blend : regs.blend_per_target) {
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blend.color_op = Regs::Blend::Equation::Add_D3D;
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blend.color_source = Regs::Blend::Factor::One_D3D;
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blend.color_dest = Regs::Blend::Factor::Zero_D3D;
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blend.alpha_op = Regs::Blend::Equation::Add_D3D;
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blend.alpha_source = Regs::Blend::Factor::One_D3D;
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blend.alpha_dest = Regs::Blend::Factor::Zero_D3D;
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}
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regs.stencil_front_op.fail = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_front_op.zfail = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_front_op.zpass = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_front_op.func = Regs::ComparisonOp::Always_GL;
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2022-10-10 21:32:38 +02:00
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regs.stencil_front_func_mask = 0xFFFFFFFF;
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regs.stencil_front_mask = 0xFFFFFFFF;
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2018-11-07 04:27:12 +01:00
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regs.stencil_two_side_enable = 1;
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2022-08-12 11:58:09 +02:00
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regs.stencil_back_op.fail = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_back_op.zfail = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_back_op.zpass = Regs::StencilOp::Op::Keep_D3D;
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regs.stencil_back_op.func = Regs::ComparisonOp::Always_GL;
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2022-10-10 21:32:38 +02:00
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regs.stencil_back_func_mask = 0xFFFFFFFF;
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regs.stencil_back_mask = 0xFFFFFFFF;
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2019-01-22 08:14:29 +01:00
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2022-08-12 11:58:09 +02:00
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regs.depth_test_func = Regs::ComparisonOp::Always_GL;
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regs.gl_front_face = Regs::FrontFace::CounterClockWise;
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regs.gl_cull_face = Regs::CullFace::Back;
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2019-07-18 01:37:01 +02:00
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2018-11-14 00:15:13 +01:00
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// TODO(Rodrigo): Most games do not set a point size. I think this is a case of a
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// register carrying a default value. Assume it's OpenGL's default (1).
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regs.point_size = 1.0f;
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2018-11-21 01:57:20 +01:00
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// TODO(bunnei): Some games do not initialize the color masks (e.g. Sonic Mania). Assuming a
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// default of enabled fixes rendering here.
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2019-05-14 14:53:16 +02:00
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for (auto& color_mask : regs.color_mask) {
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color_mask.R.Assign(1);
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color_mask.G.Assign(1);
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color_mask.B.Assign(1);
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color_mask.A.Assign(1);
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2018-11-21 01:57:20 +01:00
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}
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2019-01-22 08:14:29 +01:00
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2020-04-17 02:15:07 +02:00
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for (auto& format : regs.vertex_attrib_format) {
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format.constant.Assign(1);
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}
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2019-12-18 23:26:52 +01:00
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// NVN games expect these values to be enabled at boot
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regs.rasterize_enable = 1;
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2022-08-12 11:58:09 +02:00
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regs.color_target_mrt_enable = 1;
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2019-09-03 06:05:23 +02:00
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regs.framebuffer_srgb = 1;
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2020-05-20 06:13:40 +02:00
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regs.line_width_aliased = 1.0f;
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regs.line_width_smooth = 1.0f;
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2022-08-12 11:58:09 +02:00
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regs.gl_front_face = Maxwell3D::Regs::FrontFace::ClockWise;
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2020-05-20 03:01:25 +02:00
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regs.polygon_mode_back = Maxwell3D::Regs::PolygonMode::Fill;
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regs.polygon_mode_front = Maxwell3D::Regs::PolygonMode::Fill;
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2019-12-18 23:26:52 +01:00
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2020-03-22 07:35:11 +01:00
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shadow_state = regs;
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2018-10-26 05:42:39 +02:00
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}
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2018-02-12 03:34:20 +01:00
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2020-07-12 10:03:05 +02:00
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void Maxwell3D::ProcessMacro(u32 method, const u32* base_start, u32 amount, bool is_last_call) {
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if (executing_macro == 0) {
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// A macro call must begin by writing the macro method's register, not its argument.
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ASSERT_MSG((method % 2) == 0,
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"Can't start macro execution by writing to the ARGS register");
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executing_macro = method;
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}
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2020-07-12 10:05:04 +02:00
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macro_params.insert(macro_params.end(), base_start, base_start + amount);
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2020-07-12 10:03:05 +02:00
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// Call the macro when there are no more parameters in the command buffer
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if (is_last_call) {
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CallMacroMethod(executing_macro, macro_params);
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macro_params.clear();
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}
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}
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u32 Maxwell3D::ProcessShadowRam(u32 method, u32 argument) {
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// Keep track of the register value in shadow_state when requested.
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const auto control = shadow_state.shadow_ram_control;
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if (control == Regs::ShadowRamControl::Track ||
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control == Regs::ShadowRamControl::TrackWithFilter) {
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shadow_state.reg_array[method] = argument;
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return argument;
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}
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if (control == Regs::ShadowRamControl::Replay) {
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return shadow_state.reg_array[method];
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}
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return argument;
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}
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void Maxwell3D::ProcessDirtyRegisters(u32 method, u32 argument) {
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if (regs.reg_array[method] == argument) {
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return;
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}
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regs.reg_array[method] = argument;
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for (const auto& table : dirty.tables) {
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dirty.flags[table[method]] = true;
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}
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}
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void Maxwell3D::ProcessMethodCall(u32 method, u32 argument, u32 nonshadow_argument,
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bool is_last_call) {
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switch (method) {
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case MAXWELL3D_REG_INDEX(wait_for_idle):
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return rasterizer->WaitForIdle();
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case MAXWELL3D_REG_INDEX(shadow_ram_control):
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shadow_state.shadow_ram_control = static_cast<Regs::ShadowRamControl>(nonshadow_argument);
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return;
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(load_mme.instruction_ptr):
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return macro_engine->ClearCode(regs.load_mme.instruction_ptr);
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case MAXWELL3D_REG_INDEX(load_mme.instruction):
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return macro_engine->AddCode(regs.load_mme.instruction_ptr, argument);
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case MAXWELL3D_REG_INDEX(load_mme.start_address):
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2020-07-12 10:03:05 +02:00
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return ProcessMacroBind(argument);
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(falcon[4]):
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2020-07-12 10:03:05 +02:00
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return ProcessFirmwareCall4();
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(const_buffer.buffer):
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 1:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 2:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 3:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 4:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 5:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 6:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 7:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 8:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 9:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 10:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 11:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 12:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 13:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 14:
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case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 15:
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2022-03-15 00:11:41 +01:00
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return ProcessCBData(argument);
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(bind_groups[0].raw_config):
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2020-07-12 10:03:05 +02:00
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return ProcessCBBind(0);
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(bind_groups[1].raw_config):
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2020-07-12 10:03:05 +02:00
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return ProcessCBBind(1);
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(bind_groups[2].raw_config):
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2020-07-12 10:03:05 +02:00
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return ProcessCBBind(2);
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(bind_groups[3].raw_config):
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2020-07-12 10:03:05 +02:00
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return ProcessCBBind(3);
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(bind_groups[4].raw_config):
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2020-07-12 10:03:05 +02:00
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return ProcessCBBind(4);
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(report_semaphore.query):
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2020-07-12 10:03:05 +02:00
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return ProcessQueryGet();
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(render_enable.mode):
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2020-07-12 10:03:05 +02:00
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return ProcessQueryCondition();
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(clear_report_value):
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2020-07-12 10:03:05 +02:00
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return ProcessCounterReset();
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case MAXWELL3D_REG_INDEX(sync_info):
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return ProcessSyncPoint();
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2022-08-12 11:58:09 +02:00
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case MAXWELL3D_REG_INDEX(launch_dma):
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return upload_state.ProcessExec(regs.launch_dma.memory_layout.Value() ==
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Regs::LaunchDMA::Layout::Pitch);
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case MAXWELL3D_REG_INDEX(inline_data):
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2020-07-12 10:03:05 +02:00
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upload_state.ProcessData(argument, is_last_call);
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return;
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2020-12-30 06:25:23 +01:00
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case MAXWELL3D_REG_INDEX(fragment_barrier):
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return rasterizer->FragmentBarrier();
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2022-11-11 04:24:03 +01:00
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case MAXWELL3D_REG_INDEX(tiled_cache_barrier):
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return rasterizer->TiledCacheBarrier();
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2022-12-06 06:45:26 +01:00
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default:
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draw_manager->ProcessMethodCall(method, argument);
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break;
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2020-07-12 10:03:05 +02:00
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}
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}
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2020-06-03 08:33:38 +02:00
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void Maxwell3D::CallMacroMethod(u32 method, const std::vector<u32>& parameters) {
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2018-08-09 05:22:45 +02:00
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// Reset the current macro.
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executing_macro = 0;
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2018-10-30 04:36:03 +01:00
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// Lookup the macro offset
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2019-11-08 21:08:07 +01:00
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const u32 entry =
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((method - MacroRegistersStart) >> 1) % static_cast<u32>(macro_positions.size());
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2018-03-18 09:13:22 +01:00
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2018-08-09 05:22:45 +02:00
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// Execute the current macro.
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2022-01-25 19:41:35 +01:00
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macro_engine->Execute(macro_positions[entry], parameters);
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2022-10-21 09:38:50 +02:00
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2022-12-06 06:45:26 +01:00
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draw_manager->DrawDeferred();
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2018-03-17 02:32:44 +01:00
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}
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2020-04-28 03:47:58 +02:00
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void Maxwell3D::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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2022-10-21 09:38:50 +02:00
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// It is an error to write to a register other than the current macro's ARG register before
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// it has finished execution.
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2018-03-18 09:13:22 +01:00
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if (executing_macro != 0) {
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2019-02-26 07:01:48 +01:00
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ASSERT(method == executing_macro + 1);
|
2018-03-18 09:13:22 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
// Methods after 0xE00 are special, they're actually triggers for some microcode that was
|
|
|
|
// uploaded to the GPU during initialization.
|
2019-02-26 07:01:48 +01:00
|
|
|
if (method >= MacroRegistersStart) {
|
2020-07-12 10:03:05 +02:00
|
|
|
ProcessMacro(method, &method_argument, 1, is_last_call);
|
2018-03-18 09:13:22 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-02-26 07:01:48 +01:00
|
|
|
ASSERT_MSG(method < Regs::NUM_REGS,
|
2018-04-24 03:03:50 +02:00
|
|
|
"Invalid Maxwell3D register, increase the size of the Regs structure");
|
|
|
|
|
2022-11-21 16:38:37 +01:00
|
|
|
const u32 argument = ProcessShadowRam(method, method_argument);
|
|
|
|
ProcessDirtyRegisters(method, argument);
|
|
|
|
|
2022-12-06 06:45:26 +01:00
|
|
|
ProcessMethodCall(method, argument, method_argument, is_last_call);
|
2018-02-12 18:34:41 +01:00
|
|
|
}
|
|
|
|
|
2020-04-20 18:27:57 +02:00
|
|
|
void Maxwell3D::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
|
|
|
|
u32 methods_pending) {
|
|
|
|
// Methods after 0xE00 are special, they're actually triggers for some microcode that was
|
|
|
|
// uploaded to the GPU during initialization.
|
|
|
|
if (method >= MacroRegistersStart) {
|
2020-07-12 10:03:05 +02:00
|
|
|
ProcessMacro(method, base_start, amount, amount == methods_pending);
|
2020-04-20 18:27:57 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
switch (method) {
|
2022-08-12 11:58:09 +02:00
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer):
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 1:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 2:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 3:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 4:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 5:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 6:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 7:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 8:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 9:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 10:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 11:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 12:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 13:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 14:
|
|
|
|
case MAXWELL3D_REG_INDEX(const_buffer.buffer) + 15:
|
2022-03-15 00:11:41 +01:00
|
|
|
ProcessCBMultiData(base_start, amount);
|
2020-04-20 18:27:57 +02:00
|
|
|
break;
|
2022-08-12 11:58:09 +02:00
|
|
|
case MAXWELL3D_REG_INDEX(inline_data):
|
2022-11-29 14:04:40 +01:00
|
|
|
upload_state.ProcessData(base_start, amount);
|
2022-08-14 11:36:36 +02:00
|
|
|
return;
|
2020-07-12 10:03:05 +02:00
|
|
|
default:
|
2022-11-29 14:04:40 +01:00
|
|
|
for (u32 i = 0; i < amount; i++) {
|
|
|
|
CallMethod(method, base_start[i], methods_pending - i <= 1);
|
2020-04-20 18:27:57 +02:00
|
|
|
}
|
2020-07-12 10:03:05 +02:00
|
|
|
break;
|
2020-04-20 18:27:57 +02:00
|
|
|
}
|
2020-04-20 08:16:56 +02:00
|
|
|
}
|
|
|
|
|
2018-04-24 03:01:29 +02:00
|
|
|
void Maxwell3D::ProcessMacroUpload(u32 data) {
|
2022-08-12 11:58:09 +02:00
|
|
|
macro_engine->AddCode(regs.load_mme.instruction_ptr++, data);
|
2018-10-30 04:36:03 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void Maxwell3D::ProcessMacroBind(u32 data) {
|
2022-08-12 11:58:09 +02:00
|
|
|
macro_positions[regs.load_mme.start_address_ptr++] = data;
|
2018-04-24 03:01:29 +02:00
|
|
|
}
|
|
|
|
|
2019-08-31 22:43:19 +02:00
|
|
|
void Maxwell3D::ProcessFirmwareCall4() {
|
|
|
|
LOG_WARNING(HW_GPU, "(STUBBED) called");
|
|
|
|
|
2019-09-15 03:51:18 +02:00
|
|
|
// Firmware call 4 is a blob that changes some registers depending on its parameters.
|
|
|
|
// These registers don't affect emulation and so are stubbed by setting 0xd00 to 1.
|
2022-08-12 11:58:09 +02:00
|
|
|
regs.shadow_scratch[0] = 1;
|
2019-08-31 22:43:19 +02:00
|
|
|
}
|
|
|
|
|
2020-01-28 03:48:15 +01:00
|
|
|
void Maxwell3D::StampQueryResult(u64 payload, bool long_query) {
|
2022-08-12 11:58:09 +02:00
|
|
|
const GPUVAddr sequence_address{regs.report_semaphore.Address()};
|
2020-01-28 03:48:15 +01:00
|
|
|
if (long_query) {
|
2022-02-07 07:52:04 +01:00
|
|
|
memory_manager.Write<u64>(sequence_address + sizeof(u64), system.GPU().GetTicks());
|
|
|
|
memory_manager.Write<u64>(sequence_address, payload);
|
2020-01-28 03:48:15 +01:00
|
|
|
} else {
|
|
|
|
memory_manager.Write<u32>(sequence_address, static_cast<u32>(payload));
|
|
|
|
}
|
|
|
|
}
|
2018-02-12 18:34:41 +01:00
|
|
|
|
2020-01-28 03:48:15 +01:00
|
|
|
void Maxwell3D::ProcessQueryGet() {
|
2018-04-24 00:06:57 +02:00
|
|
|
// TODO(Subv): Support the other query units.
|
2022-08-12 11:58:09 +02:00
|
|
|
if (regs.report_semaphore.query.location != Regs::ReportSemaphore::Location::All) {
|
|
|
|
LOG_DEBUG(HW_GPU, "Locations other than ALL are unimplemented");
|
2020-05-28 23:23:25 +02:00
|
|
|
}
|
2018-04-24 00:06:57 +02:00
|
|
|
|
2022-08-12 11:58:09 +02:00
|
|
|
switch (regs.report_semaphore.query.operation) {
|
|
|
|
case Regs::ReportSemaphore::Operation::Release:
|
2022-10-19 06:21:51 +02:00
|
|
|
if (regs.report_semaphore.query.short_query != 0) {
|
2022-08-12 11:58:09 +02:00
|
|
|
const GPUVAddr sequence_address{regs.report_semaphore.Address()};
|
|
|
|
const u32 payload = regs.report_semaphore.payload;
|
2022-02-06 01:16:11 +01:00
|
|
|
std::function<void()> operation([this, sequence_address, payload] {
|
|
|
|
memory_manager.Write<u32>(sequence_address, payload);
|
|
|
|
});
|
|
|
|
rasterizer->SignalFence(std::move(operation));
|
2020-02-17 23:10:23 +01:00
|
|
|
} else {
|
2022-02-06 01:16:11 +01:00
|
|
|
struct LongQueryResult {
|
|
|
|
u64_le value;
|
|
|
|
u64_le timestamp;
|
|
|
|
};
|
2022-08-12 11:58:09 +02:00
|
|
|
const GPUVAddr sequence_address{regs.report_semaphore.Address()};
|
|
|
|
const u32 payload = regs.report_semaphore.payload;
|
2022-10-19 06:21:51 +02:00
|
|
|
[this, sequence_address, payload] {
|
2022-02-07 07:52:04 +01:00
|
|
|
memory_manager.Write<u64>(sequence_address + sizeof(u64), system.GPU().GetTicks());
|
|
|
|
memory_manager.Write<u64>(sequence_address, payload);
|
2022-10-19 06:21:51 +02:00
|
|
|
}();
|
2020-02-17 23:10:23 +01:00
|
|
|
}
|
2018-04-24 00:06:57 +02:00
|
|
|
break;
|
2022-08-12 11:58:09 +02:00
|
|
|
case Regs::ReportSemaphore::Operation::Acquire:
|
2019-07-28 00:40:10 +02:00
|
|
|
// TODO(Blinkhawk): Under this operation, the GPU waits for the CPU to write a value that
|
|
|
|
// matches the current payload.
|
2020-01-28 03:48:15 +01:00
|
|
|
UNIMPLEMENTED_MSG("Unimplemented query operation ACQUIRE");
|
|
|
|
break;
|
2022-08-12 11:58:09 +02:00
|
|
|
case Regs::ReportSemaphore::Operation::ReportOnly:
|
2019-11-26 22:52:15 +01:00
|
|
|
if (const std::optional<u64> result = GetQueryResult()) {
|
|
|
|
// If the query returns an empty optional it means it's cached and deferred.
|
|
|
|
// In this case we have a non-empty result, so we stamp it immediately.
|
2022-08-12 11:58:09 +02:00
|
|
|
StampQueryResult(*result, regs.report_semaphore.query.short_query == 0);
|
2018-06-04 02:17:31 +02:00
|
|
|
}
|
2020-01-28 03:48:15 +01:00
|
|
|
break;
|
2022-08-12 11:58:09 +02:00
|
|
|
case Regs::ReportSemaphore::Operation::Trap:
|
2020-01-28 03:48:15 +01:00
|
|
|
UNIMPLEMENTED_MSG("Unimplemented query operation TRAP");
|
|
|
|
break;
|
2019-07-28 00:40:10 +02:00
|
|
|
default:
|
2020-01-28 03:48:15 +01:00
|
|
|
UNIMPLEMENTED_MSG("Unknown query operation");
|
2018-02-12 18:34:41 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2018-03-05 01:13:15 +01:00
|
|
|
|
2019-07-01 04:21:28 +02:00
|
|
|
void Maxwell3D::ProcessQueryCondition() {
|
2022-08-12 11:58:09 +02:00
|
|
|
const GPUVAddr condition_address{regs.render_enable.Address()};
|
2022-11-30 02:43:36 +01:00
|
|
|
switch (regs.render_enable_override) {
|
|
|
|
case Regs::RenderEnable::Override::AlwaysRender:
|
2019-07-01 04:21:28 +02:00
|
|
|
execute_on = true;
|
|
|
|
break;
|
2022-11-30 02:43:36 +01:00
|
|
|
case Regs::RenderEnable::Override::NeverRender:
|
2019-07-01 04:21:28 +02:00
|
|
|
execute_on = false;
|
|
|
|
break;
|
2022-11-30 02:43:36 +01:00
|
|
|
case Regs::RenderEnable::Override::UseRenderEnable:
|
|
|
|
switch (regs.render_enable.mode) {
|
|
|
|
case Regs::RenderEnable::Mode::True: {
|
|
|
|
execute_on = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Regs::RenderEnable::Mode::False: {
|
|
|
|
execute_on = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Regs::RenderEnable::Mode::Conditional: {
|
|
|
|
Regs::ReportSemaphore::Compare cmp;
|
|
|
|
memory_manager.ReadBlock(condition_address, &cmp, sizeof(cmp));
|
|
|
|
execute_on = cmp.initial_sequence != 0U && cmp.initial_mode != 0U;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Regs::RenderEnable::Mode::IfEqual: {
|
|
|
|
Regs::ReportSemaphore::Compare cmp;
|
|
|
|
memory_manager.ReadBlock(condition_address, &cmp, sizeof(cmp));
|
|
|
|
execute_on = cmp.initial_sequence == cmp.current_sequence &&
|
|
|
|
cmp.initial_mode == cmp.current_mode;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Regs::RenderEnable::Mode::IfNotEqual: {
|
|
|
|
Regs::ReportSemaphore::Compare cmp;
|
|
|
|
memory_manager.ReadBlock(condition_address, &cmp, sizeof(cmp));
|
|
|
|
execute_on = cmp.initial_sequence != cmp.current_sequence ||
|
|
|
|
cmp.initial_mode != cmp.current_mode;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: {
|
|
|
|
UNIMPLEMENTED_MSG("Uninplemented Condition Mode!");
|
|
|
|
execute_on = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2019-07-01 04:21:28 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-28 00:40:10 +02:00
|
|
|
void Maxwell3D::ProcessCounterReset() {
|
2022-08-12 11:58:09 +02:00
|
|
|
switch (regs.clear_report_value) {
|
|
|
|
case Regs::ClearReport::ZPassPixelCount:
|
2020-06-11 05:58:57 +02:00
|
|
|
rasterizer->ResetCounter(QueryType::SamplesPassed);
|
2019-07-28 00:40:10 +02:00
|
|
|
break;
|
|
|
|
default:
|
2022-08-12 11:58:09 +02:00
|
|
|
LOG_DEBUG(Render_OpenGL, "Unimplemented counter reset={}", regs.clear_report_value);
|
2019-07-28 00:40:10 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-04-02 17:46:00 +02:00
|
|
|
void Maxwell3D::ProcessSyncPoint() {
|
|
|
|
const u32 sync_point = regs.sync_info.sync_point.Value();
|
2022-11-24 14:02:58 +01:00
|
|
|
[[maybe_unused]] const u32 cache_flush = regs.sync_info.clean_l2.Value();
|
2022-10-19 06:21:51 +02:00
|
|
|
rasterizer->SignalSyncPoint(sync_point);
|
2019-04-02 17:46:00 +02:00
|
|
|
}
|
|
|
|
|
2019-11-26 22:52:15 +01:00
|
|
|
std::optional<u64> Maxwell3D::GetQueryResult() {
|
2022-08-12 11:58:09 +02:00
|
|
|
switch (regs.report_semaphore.query.report) {
|
|
|
|
case Regs::ReportSemaphore::Report::Payload:
|
|
|
|
return regs.report_semaphore.payload;
|
|
|
|
case Regs::ReportSemaphore::Report::ZPassPixelCount64:
|
2019-11-26 22:52:15 +01:00
|
|
|
// Deferred.
|
2022-08-12 11:58:09 +02:00
|
|
|
rasterizer->Query(regs.report_semaphore.Address(), QueryType::SamplesPassed,
|
2020-06-11 05:58:57 +02:00
|
|
|
system.GPU().GetTicks());
|
2020-09-22 23:31:53 +02:00
|
|
|
return std::nullopt;
|
2019-11-26 22:52:15 +01:00
|
|
|
default:
|
2022-08-12 11:58:09 +02:00
|
|
|
LOG_DEBUG(HW_GPU, "Unimplemented query report type {}",
|
|
|
|
regs.report_semaphore.query.report.Value());
|
2019-11-26 22:52:15 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-01-17 00:48:58 +01:00
|
|
|
void Maxwell3D::ProcessCBBind(size_t stage_index) {
|
2018-03-17 23:06:23 +01:00
|
|
|
// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
|
2022-08-12 11:58:09 +02:00
|
|
|
const auto& bind_data = regs.bind_groups[stage_index];
|
|
|
|
auto& buffer = state.shader_stages[stage_index].const_buffers[bind_data.shader_slot];
|
2018-03-17 23:06:23 +01:00
|
|
|
buffer.enabled = bind_data.valid.Value() != 0;
|
2022-08-12 11:58:09 +02:00
|
|
|
buffer.address = regs.const_buffer.Address();
|
|
|
|
buffer.size = regs.const_buffer.size;
|
2021-01-17 00:48:58 +01:00
|
|
|
|
|
|
|
const bool is_enabled = bind_data.valid.Value() != 0;
|
2021-06-01 19:26:43 +02:00
|
|
|
if (!is_enabled) {
|
2022-08-12 11:58:09 +02:00
|
|
|
rasterizer->DisableGraphicsUniformBuffer(stage_index, bind_data.shader_slot);
|
2021-06-01 19:26:43 +02:00
|
|
|
return;
|
|
|
|
}
|
2022-08-12 11:58:09 +02:00
|
|
|
const GPUVAddr gpu_addr = regs.const_buffer.Address();
|
|
|
|
const u32 size = regs.const_buffer.size;
|
|
|
|
rasterizer->BindGraphicsUniformBuffer(stage_index, bind_data.shader_slot, gpu_addr, size);
|
2018-03-17 04:06:24 +01:00
|
|
|
}
|
2018-03-17 02:32:44 +01:00
|
|
|
|
2022-03-15 00:11:41 +01:00
|
|
|
void Maxwell3D::ProcessCBMultiData(const u32* start_base, u32 amount) {
|
2018-03-18 21:19:47 +01:00
|
|
|
// Write the input value to the current const buffer at the current position.
|
2022-08-12 11:58:09 +02:00
|
|
|
const GPUVAddr buffer_address = regs.const_buffer.Address();
|
2018-03-18 21:19:47 +01:00
|
|
|
ASSERT(buffer_address != 0);
|
|
|
|
|
|
|
|
// Don't allow writing past the end of the buffer.
|
2022-08-12 11:58:09 +02:00
|
|
|
ASSERT(regs.const_buffer.offset <= regs.const_buffer.size);
|
2018-03-18 21:19:47 +01:00
|
|
|
|
2022-08-12 11:58:09 +02:00
|
|
|
const GPUVAddr address{buffer_address + regs.const_buffer.offset};
|
2022-03-15 00:11:41 +01:00
|
|
|
const size_t copy_size = amount * sizeof(u32);
|
|
|
|
memory_manager.WriteBlock(address, start_base, copy_size);
|
2018-03-18 21:19:47 +01:00
|
|
|
|
2022-03-15 00:11:41 +01:00
|
|
|
// Increment the current buffer position.
|
2022-08-12 11:58:09 +02:00
|
|
|
regs.const_buffer.offset += static_cast<u32>(copy_size);
|
2022-03-15 00:11:41 +01:00
|
|
|
}
|
2019-02-19 02:58:32 +01:00
|
|
|
|
2022-03-15 00:11:41 +01:00
|
|
|
void Maxwell3D::ProcessCBData(u32 value) {
|
|
|
|
ProcessCBMultiData(&value, 1);
|
2018-03-18 21:19:47 +01:00
|
|
|
}
|
|
|
|
|
2018-03-26 22:46:49 +02:00
|
|
|
Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
|
2022-08-12 11:58:09 +02:00
|
|
|
const GPUVAddr tic_address_gpu{regs.tex_header.Address() +
|
|
|
|
tic_index * sizeof(Texture::TICEntry)};
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2018-03-26 22:46:49 +02:00
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Texture::TICEntry tic_entry;
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2019-04-16 05:05:05 +02:00
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memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry));
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2018-03-26 22:46:49 +02:00
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return tic_entry;
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}
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Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
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2022-08-12 11:58:09 +02:00
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const GPUVAddr tsc_address_gpu{regs.tex_sampler.Address() +
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tsc_index * sizeof(Texture::TSCEntry)};
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2018-03-26 22:46:49 +02:00
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Texture::TSCEntry tsc_entry;
|
2019-04-16 05:05:05 +02:00
|
|
|
memory_manager.ReadBlockUnsafe(tsc_address_gpu, &tsc_entry, sizeof(Texture::TSCEntry));
|
2018-03-26 22:46:49 +02:00
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return tsc_entry;
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}
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2018-03-28 22:14:47 +02:00
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u32 Maxwell3D::GetRegisterValue(u32 method) const {
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ASSERT_MSG(method < Regs::NUM_REGS, "Invalid Maxwell3D register");
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return regs.reg_array[method];
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}
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2018-10-20 21:58:06 +02:00
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} // namespace Tegra::Engines
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