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https://github.com/yuzu-emu/yuzu-android.git
synced 2024-11-24 04:55:47 +01:00
shader: Implement TEXS
This commit is contained in:
ReinUsesLisp
ameerj
parent
71f96fa636
commit
17a82b56d7
@ -102,7 +102,8 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/predicate_set_predicate.cpp
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frontend/maxwell/translate/impl/predicate_set_register.cpp
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frontend/maxwell/translate/impl/select_source_with_predicate.cpp
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frontend/maxwell/translate/impl/texture_sample.cpp
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frontend/maxwell/translate/impl/texture_fetch.cpp
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frontend/maxwell/translate/impl/texture_fetch_swizzled.cpp
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frontend/maxwell/translate/translate.cpp
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frontend/maxwell/translate/translate.h
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ir_opt/collect_shader_info_pass.cpp
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@ -57,18 +57,27 @@ Id Texture(EmitContext& ctx, const IR::Value& index) {
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throw NotImplementedException("Indirect texture sample");
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}
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Id Decorate(EmitContext& ctx, IR::Inst* inst, Id sample) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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if (info.relaxed_precision != 0) {
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ctx.Decorate(sample, spv::Decoration::RelaxedPrecision);
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}
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return sample;
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}
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template <typename MethodPtrType, typename... Args>
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Id Emit(MethodPtrType sparse_ptr, MethodPtrType non_sparse_ptr, EmitContext& ctx, IR::Inst* inst,
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Id result_type, Args&&... args) {
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IR::Inst* const sparse{inst->GetAssociatedPseudoOperation(IR::Opcode::GetSparseFromOp)};
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if (!sparse) {
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return (ctx.*non_sparse_ptr)(result_type, std::forward<Args>(args)...);
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return Decorate(ctx, inst, (ctx.*non_sparse_ptr)(result_type, std::forward<Args>(args)...));
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}
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const Id struct_type{ctx.TypeStruct(ctx.U32[1], result_type)};
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const Id sample{(ctx.*sparse_ptr)(struct_type, std::forward<Args>(args)...)};
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const Id resident_code{ctx.OpCompositeExtract(ctx.U32[1], sample, 0U)};
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sparse->SetDefinition(ctx.OpImageSparseTexelsResident(ctx.U1, resident_code));
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sparse->Invalidate();
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Decorate(ctx, inst, sample);
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return ctx.OpCompositeExtract(result_type, sample, 1U);
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}
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} // Anonymous namespace
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@ -512,6 +512,14 @@ Value IREmitter::UnpackFloat2x16(const U32& value) {
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return Inst(Opcode::UnpackFloat2x16, value);
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}
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U32 IREmitter::PackHalf2x16(const Value& vector) {
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return Inst<U32>(Opcode::PackHalf2x16, vector);
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}
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Value IREmitter::UnpackHalf2x16(const U32& value) {
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return Inst(Opcode::UnpackHalf2x16, value);
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}
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F64 IREmitter::PackDouble2x32(const Value& vector) {
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return Inst<F64>(Opcode::PackDouble2x32, vector);
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}
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@ -115,6 +115,9 @@ public:
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[[nodiscard]] U32 PackFloat2x16(const Value& vector);
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[[nodiscard]] Value UnpackFloat2x16(const U32& value);
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[[nodiscard]] U32 PackHalf2x16(const Value& vector);
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[[nodiscard]] Value UnpackHalf2x16(const U32& value);
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[[nodiscard]] F64 PackDouble2x32(const Value& vector);
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[[nodiscard]] Value UnpackDouble2x32(const F64& value);
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@ -36,7 +36,8 @@ union TextureInstInfo {
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u32 raw;
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BitField<0, 8, TextureType> type;
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BitField<8, 1, u32> has_bias;
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BitField<16, 1, u32> has_lod_clamp;
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BitField<9, 1, u32> has_lod_clamp;
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BitField<10, 1, u32> relaxed_precision;
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};
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static_assert(sizeof(TextureInstInfo) <= sizeof(u32));
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@ -553,10 +553,6 @@ void TranslatorVisitor::SYNC(u64) {
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ThrowNotImplemented(Opcode::SYNC);
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}
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void TranslatorVisitor::TEXS(u64) {
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ThrowNotImplemented(Opcode::TEXS);
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}
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void TranslatorVisitor::TLD(u64) {
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ThrowNotImplemented(Opcode::TLD);
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}
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@ -0,0 +1,262 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <utility>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Precision : u64 {
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F16,
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F32,
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};
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union Encoding {
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u64 raw;
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BitField<59, 1, Precision> precision;
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BitField<53, 4, u64> encoding;
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BitField<49, 1, u64> nodep;
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BitField<28, 8, IR::Reg> dest_reg_b;
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BitField<0, 8, IR::Reg> dest_reg_a;
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<20, 8, IR::Reg> src_reg_b;
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BitField<36, 13, u64> cbuf_offset;
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BitField<50, 3, u64> swizzle;
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};
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constexpr unsigned R = 1;
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constexpr unsigned G = 2;
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constexpr unsigned B = 4;
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constexpr unsigned A = 8;
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constexpr std::array RG_LUT{
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R, //
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G, //
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B, //
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A, //
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R | G, //
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R | A, //
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G | A, //
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B | A, //
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};
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constexpr std::array RGBA_LUT{
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R | G | B, //
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R | G | A, //
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R | B | A, //
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G | B | A, //
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R | G | B | A, //
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};
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void CheckAlignment(IR::Reg reg, int alignment) {
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if (!IR::IsAligned(reg, alignment)) {
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throw NotImplementedException("Unaligned source register {}", reg);
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}
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}
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template <typename... Args>
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IR::Value Composite(TranslatorVisitor& v, Args... regs) {
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return v.ir.CompositeConstruct(v.F(regs)...);
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}
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IR::F32 ReadArray(TranslatorVisitor& v, const IR::U32& value) {
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return v.ir.ConvertUToF(32, v.ir.BitFieldExtract(value, v.ir.Imm32(0), v.ir.Imm32(16)));
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}
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IR::Value Sample(TranslatorVisitor& v, u64 insn) {
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const Encoding texs{insn};
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const IR::U32 handle{v.ir.Imm32(static_cast<u32>(texs.cbuf_offset))};
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const IR::F32 zero{v.ir.Imm32(0.0f)};
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const IR::Reg reg_a{texs.src_reg_a};
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const IR::Reg reg_b{texs.src_reg_b};
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IR::TextureInstInfo info{};
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if (texs.precision == Precision::F16) {
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info.relaxed_precision.Assign(1);
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}
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switch (texs.encoding) {
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case 0: // 1D.LZ
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info.type.Assign(TextureType::Color1D);
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return v.ir.ImageSampleExplicitLod(handle, v.F(reg_a), zero, {}, {}, info);
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case 1: // 2D
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info.type.Assign(TextureType::Color2D);
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return v.ir.ImageSampleImplicitLod(handle, Composite(v, reg_a, reg_b), {}, {}, {}, info);
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case 2: // 2D.LZ
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info.type.Assign(TextureType::Color2D);
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return v.ir.ImageSampleExplicitLod(handle, Composite(v, reg_a, reg_b), zero, {}, {}, info);
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case 3: // 2D.LL
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CheckAlignment(reg_a, 2);
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info.type.Assign(TextureType::Color2D);
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return v.ir.ImageSampleExplicitLod(handle, Composite(v, reg_a, reg_a + 1), v.F(reg_b), {},
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{}, info);
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case 4: // 2D.DC
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CheckAlignment(reg_a, 2);
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info.type.Assign(TextureType::Shadow2D);
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return v.ir.ImageSampleDrefImplicitLod(handle, Composite(v, reg_a, reg_a + 1), v.F(reg_b),
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{}, {}, {}, info);
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case 5: // 2D.LL.DC
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CheckAlignment(reg_a, 2);
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CheckAlignment(reg_b, 2);
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info.type.Assign(TextureType::Shadow2D);
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return v.ir.ImageSampleDrefExplicitLod(handle, Composite(v, reg_a, reg_a + 1),
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v.F(reg_b + 1), v.F(reg_b), {}, {}, info);
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case 6: // 2D.LZ.DC
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CheckAlignment(reg_a, 2);
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info.type.Assign(TextureType::Shadow2D);
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return v.ir.ImageSampleDrefExplicitLod(handle, Composite(v, reg_a, reg_a + 1), v.F(reg_b),
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zero, {}, {}, info);
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case 7: // ARRAY_2D
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CheckAlignment(reg_a, 2);
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info.type.Assign(TextureType::ColorArray2D);
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return v.ir.ImageSampleImplicitLod(
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handle, v.ir.CompositeConstruct(v.F(reg_a + 1), v.F(reg_b), ReadArray(v, v.X(reg_a))),
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{}, {}, {}, info);
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case 8: // ARRAY_2D.LZ
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CheckAlignment(reg_a, 2);
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info.type.Assign(TextureType::ColorArray2D);
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return v.ir.ImageSampleExplicitLod(
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handle, v.ir.CompositeConstruct(v.F(reg_a + 1), v.F(reg_b), ReadArray(v, v.X(reg_a))),
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zero, {}, {}, info);
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case 9: // ARRAY_2D.LZ.DC
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CheckAlignment(reg_a, 2);
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CheckAlignment(reg_b, 2);
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info.type.Assign(TextureType::ShadowArray2D);
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return v.ir.ImageSampleDrefExplicitLod(
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handle, v.ir.CompositeConstruct(v.F(reg_a + 1), v.F(reg_b), ReadArray(v, v.X(reg_a))),
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v.F(reg_b + 1), zero, {}, {}, info);
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case 10: // 3D
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CheckAlignment(reg_a, 2);
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info.type.Assign(TextureType::Color3D);
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return v.ir.ImageSampleImplicitLod(handle, Composite(v, reg_a, reg_a + 1, reg_b), {}, {},
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{}, info);
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case 11: // 3D.LZ
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CheckAlignment(reg_a, 2);
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info.type.Assign(TextureType::Color3D);
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return v.ir.ImageSampleExplicitLod(handle, Composite(v, reg_a, reg_a + 1, reg_b), zero, {},
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{}, info);
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case 12: // CUBE
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CheckAlignment(reg_a, 2);
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info.type.Assign(TextureType::ColorCube);
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return v.ir.ImageSampleImplicitLod(handle, Composite(v, reg_a, reg_a + 1, reg_b), {}, {},
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{}, info);
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case 13: // CUBE.LL
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CheckAlignment(reg_a, 2);
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CheckAlignment(reg_b, 2);
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info.type.Assign(TextureType::ColorCube);
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return v.ir.ImageSampleExplicitLod(handle, Composite(v, reg_a, reg_a + 1, reg_b),
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v.F(reg_b + 1), {}, {}, info);
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default:
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throw NotImplementedException("Illegal encoding {}", texs.encoding.Value());
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}
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}
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unsigned Swizzle(u64 insn) {
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const Encoding texs{insn};
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const size_t encoding{texs.swizzle};
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if (texs.dest_reg_b == IR::Reg::RZ) {
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if (encoding >= RG_LUT.size()) {
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throw NotImplementedException("Illegal RG encoding {}", encoding);
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}
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return RG_LUT[encoding];
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} else {
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if (encoding >= RGBA_LUT.size()) {
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throw NotImplementedException("Illegal RGBA encoding {}", encoding);
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}
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return RGBA_LUT[encoding];
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}
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}
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IR::F32 Extract(TranslatorVisitor& v, const IR::Value& sample, unsigned component) {
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const bool is_shadow{sample.Type() == IR::Type::F32};
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if (is_shadow) {
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const bool is_alpha{component == 3};
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return is_alpha ? v.ir.Imm32(1.0f) : IR::F32{sample};
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} else {
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return IR::F32{v.ir.CompositeExtract(sample, component)};
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}
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}
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IR::Reg RegStoreComponent32(u64 insn, unsigned index) {
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const Encoding texs{insn};
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switch (index) {
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case 0:
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return texs.dest_reg_a;
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case 1:
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CheckAlignment(texs.dest_reg_a, 2);
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return texs.dest_reg_a + 1;
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case 2:
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return texs.dest_reg_b;
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case 3:
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CheckAlignment(texs.dest_reg_b, 2);
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return texs.dest_reg_b + 1;
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}
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throw LogicError("Invalid store index {}", index);
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}
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void Store32(TranslatorVisitor& v, u64 insn, const IR::Value& sample) {
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const unsigned swizzle{Swizzle(insn)};
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unsigned store_index{0};
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for (unsigned component = 0; component < 4; ++component) {
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if (((swizzle >> component) & 1) == 0) {
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continue;
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}
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const IR::Reg dest{RegStoreComponent32(insn, store_index)};
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v.F(dest, Extract(v, sample, component));
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++store_index;
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}
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}
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IR::U32 Pack(TranslatorVisitor& v, const IR::F32& lhs, const IR::F32& rhs) {
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return v.ir.PackHalf2x16(v.ir.CompositeConstruct(lhs, rhs));
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}
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void Store16(TranslatorVisitor& v, u64 insn, const IR::Value& sample) {
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const unsigned swizzle{Swizzle(insn)};
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unsigned store_index{0};
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std::array<IR::F32, 4> swizzled;
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for (unsigned component = 0; component < 4; ++component) {
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if (((swizzle >> component) & 1) == 0) {
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continue;
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}
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swizzled[store_index] = Extract(v, sample, component);
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++store_index;
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}
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const IR::F32 zero{v.ir.Imm32(0.0f)};
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const Encoding texs{insn};
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switch (store_index) {
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case 1:
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v.X(texs.dest_reg_a, Pack(v, swizzled[0], zero));
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break;
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case 2:
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case 3:
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case 4:
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v.X(texs.dest_reg_a, Pack(v, swizzled[0], swizzled[1]));
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switch (store_index) {
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case 2:
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break;
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case 3:
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v.X(texs.dest_reg_b, Pack(v, swizzled[2], zero));
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break;
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case 4:
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v.X(texs.dest_reg_b, Pack(v, swizzled[2], swizzled[3]));
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break;
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}
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break;
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}
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}
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} // Anonymous namespace
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void TranslatorVisitor::TEXS(u64 insn) {
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const IR::Value sample{Sample(*this, insn)};
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if (Encoding{insn}.precision == Precision::F32) {
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Store32(*this, insn, sample);
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} else {
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Store16(*this, insn, sample);
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}
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}
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} // namespace Shader::Maxwell
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