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shader: Implement IADD3
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c2155f04d4
commit
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@ -74,6 +74,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/impl.cpp
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frontend/maxwell/translate/impl/impl.h
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frontend/maxwell/translate/impl/integer_add.cpp
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frontend/maxwell/translate/impl/integer_add_three_input.cpp
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frontend/maxwell/translate/impl/integer_compare.cpp
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frontend/maxwell/translate/impl/integer_compare_and_set.cpp
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frontend/maxwell/translate/impl/integer_minimum_maximum.cpp
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@ -0,0 +1,103 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Shift : u64 {
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None,
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Right,
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Left,
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};
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enum class Half : u64 {
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All,
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Lower,
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Upper,
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};
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[[nodiscard]] IR::U32 IntegerHalf(IR::IREmitter& ir, const IR::U32& value, Half half) {
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constexpr bool is_signed{false};
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switch (half) {
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case Half::Lower:
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return ir.BitFieldExtract(value, ir.Imm32(0), ir.Imm32(16), is_signed);
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case Half::Upper:
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return ir.BitFieldExtract(value, ir.Imm32(16), ir.Imm32(16), is_signed);
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default:
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return value;
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}
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}
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[[nodiscard]] IR::U32 IntegerShift(IR::IREmitter& ir, const IR::U32& value, Shift shift) {
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switch (shift) {
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case Shift::Right:
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return ir.ShiftRightLogical(value, ir.Imm32(16));
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case Shift::Left:
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return ir.ShiftLeftLogical(value, ir.Imm32(16));
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default:
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return value;
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}
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}
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void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a;
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BitField<31, 2, Half> half_c;
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BitField<33, 2, Half> half_b;
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BitField<35, 2, Half> half_a;
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BitField<37, 2, Shift> shift;
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BitField<47, 1, u64> cc;
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BitField<48, 1, u64> x;
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BitField<49, 1, u64> neg_c;
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BitField<50, 1, u64> neg_b;
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BitField<51, 1, u64> neg_a;
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} iadd3{insn};
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if (iadd3.x != 0) {
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throw NotImplementedException("IADD3 X");
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}
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if (iadd3.cc != 0) {
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throw NotImplementedException("IADD3 CC");
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}
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IR::U32 op_a{v.X(iadd3.src_a)};
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op_a = IntegerHalf(v.ir, op_a, iadd3.half_a);
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op_b = IntegerHalf(v.ir, op_b, iadd3.half_b);
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op_c = IntegerHalf(v.ir, op_c, iadd3.half_c);
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if (iadd3.neg_a != 0) {
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op_a = v.ir.INeg(op_a);
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}
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if (iadd3.neg_b != 0) {
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op_b = v.ir.INeg(op_b);
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}
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if (iadd3.neg_c != 0) {
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op_c = v.ir.INeg(op_c);
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}
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IR::U32 lhs{v.ir.IAdd(op_a, op_b)};
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lhs = IntegerShift(v.ir, lhs, iadd3.shift);
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const IR::U32 result{v.ir.IAdd(lhs, op_c)};
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v.X(iadd3.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::IADD3_reg(u64 insn) {
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IADD3(*this, insn, GetReg20(insn), GetReg39(insn));
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}
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void TranslatorVisitor::IADD3_cbuf(u64 insn) {
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IADD3(*this, insn, GetCbuf(insn), GetReg39(insn));
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}
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void TranslatorVisitor::IADD3_imm(u64 insn) {
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IADD3(*this, insn, GetImm20(insn), GetReg39(insn));
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}
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} // namespace Shader::Maxwell
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@ -365,18 +365,6 @@ void TranslatorVisitor::I2I_imm(u64) {
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ThrowNotImplemented(Opcode::I2I_imm);
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}
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void TranslatorVisitor::IADD3_reg(u64) {
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ThrowNotImplemented(Opcode::IADD3_reg);
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}
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void TranslatorVisitor::IADD3_cbuf(u64) {
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ThrowNotImplemented(Opcode::IADD3_cbuf);
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}
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void TranslatorVisitor::IADD3_imm(u64) {
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ThrowNotImplemented(Opcode::IADD3_imm);
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}
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void TranslatorVisitor::IDE(u64) {
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ThrowNotImplemented(Opcode::IDE);
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}
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