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Merge pull request #9252 from liamwhite/radv-superiority
maxwell3d: HLE multi-layer clear macro
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commit
4975f60162
@ -232,7 +232,7 @@ void Maxwell3D::ProcessMethodCall(u32 method, u32 argument, u32 nonshadow_argume
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use_topology_override = true;
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use_topology_override = true;
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return;
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return;
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case MAXWELL3D_REG_INDEX(clear_surface):
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case MAXWELL3D_REG_INDEX(clear_surface):
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return ProcessClearBuffers();
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return ProcessClearBuffers(1);
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case MAXWELL3D_REG_INDEX(report_semaphore.query):
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case MAXWELL3D_REG_INDEX(report_semaphore.query):
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return ProcessQueryGet();
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return ProcessQueryGet();
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case MAXWELL3D_REG_INDEX(render_enable.mode):
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case MAXWELL3D_REG_INDEX(render_enable.mode):
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@ -596,8 +596,8 @@ u32 Maxwell3D::GetRegisterValue(u32 method) const {
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return regs.reg_array[method];
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return regs.reg_array[method];
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}
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}
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void Maxwell3D::ProcessClearBuffers() {
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void Maxwell3D::ProcessClearBuffers(u32 layer_count) {
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rasterizer->Clear();
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rasterizer->Clear(layer_count);
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}
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}
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void Maxwell3D::ProcessDraw(u32 instance_count) {
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void Maxwell3D::ProcessDraw(u32 instance_count) {
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@ -3086,6 +3086,9 @@ public:
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std::vector<u8> inline_index_draw_indexes;
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std::vector<u8> inline_index_draw_indexes;
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/// Handles a write to the CLEAR_BUFFERS register.
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void ProcessClearBuffers(u32 layer_count);
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private:
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private:
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void InitializeRegisterDefaults();
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void InitializeRegisterDefaults();
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@ -3120,9 +3123,6 @@ private:
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/// Handles firmware blob 4
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/// Handles firmware blob 4
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void ProcessFirmwareCall4();
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void ProcessFirmwareCall4();
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/// Handles a write to the CLEAR_BUFFERS register.
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void ProcessClearBuffers();
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/// Handles a write to the QUERY_GET register.
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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void ProcessQueryGet();
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@ -126,11 +126,25 @@ void HLE_3F5E74B9C9A50164(Engines::Maxwell3D& maxwell3d, const std::vector<u32>&
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}
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}
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}
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}
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constexpr std::array<std::pair<u64, HLEFunction>, 4> hle_funcs{{
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// Multi-layer Clear
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void HLE_EAD26C3E2109B06B(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
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ASSERT(parameters.size() == 1);
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const Engines::Maxwell3D::Regs::ClearSurface clear_params{parameters[0]};
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const u32 rt_index = clear_params.RT;
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const u32 num_layers = maxwell3d.regs.rt[rt_index].depth;
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ASSERT(clear_params.layer == 0);
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maxwell3d.regs.clear_surface.raw = clear_params.raw;
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maxwell3d.ProcessClearBuffers(num_layers);
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}
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constexpr std::array<std::pair<u64, HLEFunction>, 5> hle_funcs{{
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{0x771BB18C62444DA0, &HLE_771BB18C62444DA0},
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{0x771BB18C62444DA0, &HLE_771BB18C62444DA0},
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{0x0D61FC9FAAC9FCAD, &HLE_0D61FC9FAAC9FCAD},
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{0x0D61FC9FAAC9FCAD, &HLE_0D61FC9FAAC9FCAD},
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{0x0217920100488FF7, &HLE_0217920100488FF7},
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{0x0217920100488FF7, &HLE_0217920100488FF7},
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{0x3F5E74B9C9A50164, &HLE_3F5E74B9C9A50164},
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{0x3F5E74B9C9A50164, &HLE_3F5E74B9C9A50164},
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{0xEAD26C3E2109B06B, &HLE_EAD26C3E2109B06B},
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}};
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}};
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class HLEMacroImpl final : public CachedMacro {
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class HLEMacroImpl final : public CachedMacro {
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@ -43,7 +43,7 @@ public:
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virtual void Draw(bool is_indexed, u32 instance_count) = 0;
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virtual void Draw(bool is_indexed, u32 instance_count) = 0;
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/// Clear the current framebuffer
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/// Clear the current framebuffer
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virtual void Clear() = 0;
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virtual void Clear(u32 layer_count) = 0;
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/// Dispatches a compute shader invocation
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/// Dispatches a compute shader invocation
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virtual void DispatchCompute() = 0;
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virtual void DispatchCompute() = 0;
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@ -136,7 +136,7 @@ void RasterizerOpenGL::LoadDiskResources(u64 title_id, std::stop_token stop_load
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shader_cache.LoadDiskResources(title_id, stop_loading, callback);
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shader_cache.LoadDiskResources(title_id, stop_loading, callback);
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}
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}
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void RasterizerOpenGL::Clear() {
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void RasterizerOpenGL::Clear(u32 layer_count) {
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MICROPROFILE_SCOPE(OpenGL_Clears);
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MICROPROFILE_SCOPE(OpenGL_Clears);
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if (!maxwell3d->ShouldExecute()) {
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if (!maxwell3d->ShouldExecute()) {
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return;
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return;
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@ -69,7 +69,7 @@ public:
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~RasterizerOpenGL() override;
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~RasterizerOpenGL() override;
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void Draw(bool is_indexed, u32 instance_count) override;
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void Draw(bool is_indexed, u32 instance_count) override;
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void Clear() override;
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void Clear(u32 layer_count) override;
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void DispatchCompute() override;
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void DispatchCompute() override;
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void ResetCounter(VideoCore::QueryType type) override;
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void ResetCounter(VideoCore::QueryType type) override;
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void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override;
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void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override;
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@ -213,7 +213,7 @@ void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
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EndTransformFeedback();
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EndTransformFeedback();
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}
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}
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void RasterizerVulkan::Clear() {
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void RasterizerVulkan::Clear(u32 layer_count) {
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MICROPROFILE_SCOPE(Vulkan_Clearing);
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MICROPROFILE_SCOPE(Vulkan_Clearing);
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if (!maxwell3d->ShouldExecute()) {
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if (!maxwell3d->ShouldExecute()) {
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@ -256,7 +256,7 @@ void RasterizerVulkan::Clear() {
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.rect = regs.clear_control.use_scissor ? GetScissorState(regs, 0, up_scale, down_shift)
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.rect = regs.clear_control.use_scissor ? GetScissorState(regs, 0, up_scale, down_shift)
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: default_scissor,
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: default_scissor,
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.baseArrayLayer = regs.clear_surface.layer,
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.baseArrayLayer = regs.clear_surface.layer,
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.layerCount = 1,
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.layerCount = layer_count,
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};
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};
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if (clear_rect.rect.extent.width == 0 || clear_rect.rect.extent.height == 0) {
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if (clear_rect.rect.extent.width == 0 || clear_rect.rect.extent.height == 0) {
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return;
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return;
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@ -65,7 +65,7 @@ public:
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~RasterizerVulkan() override;
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~RasterizerVulkan() override;
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void Draw(bool is_indexed, u32 instance_count) override;
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void Draw(bool is_indexed, u32 instance_count) override;
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void Clear() override;
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void Clear(u32 layer_count) override;
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void DispatchCompute() override;
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void DispatchCompute() override;
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void ResetCounter(VideoCore::QueryType type) override;
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void ResetCounter(VideoCore::QueryType type) override;
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void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override;
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void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override;
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