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Merge pull request #4070 from ogniK5377/GetTPCMasks-fix
nvdrv: Fix GetTPCMasks for ioctl3
This commit is contained in:
commit
55ebf68636
@ -25,7 +25,7 @@ u32 nvhost_ctrl_gpu::ioctl(Ioctl command, const std::vector<u8>& input,
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case IoctlCommand::IocGetCharacteristicsCommand:
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case IoctlCommand::IocGetCharacteristicsCommand:
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return GetCharacteristics(input, output, output2, version);
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return GetCharacteristics(input, output, output2, version);
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case IoctlCommand::IocGetTPCMasksCommand:
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case IoctlCommand::IocGetTPCMasksCommand:
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return GetTPCMasks(input, output);
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return GetTPCMasks(input, output, output2, version);
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case IoctlCommand::IocGetActiveSlotMaskCommand:
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case IoctlCommand::IocGetActiveSlotMaskCommand:
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return GetActiveSlotMask(input, output);
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return GetActiveSlotMask(input, output);
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case IoctlCommand::IocZcullGetCtxSizeCommand:
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case IoctlCommand::IocZcullGetCtxSizeCommand:
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@ -98,17 +98,22 @@ u32 nvhost_ctrl_gpu::GetCharacteristics(const std::vector<u8>& input, std::vecto
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return 0;
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return 0;
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}
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}
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u32 nvhost_ctrl_gpu::GetTPCMasks(const std::vector<u8>& input, std::vector<u8>& output) {
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u32 nvhost_ctrl_gpu::GetTPCMasks(const std::vector<u8>& input, std::vector<u8>& output,
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std::vector<u8>& output2, IoctlVersion version) {
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IoctlGpuGetTpcMasksArgs params{};
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IoctlGpuGetTpcMasksArgs params{};
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std::memcpy(¶ms, input.data(), input.size());
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std::memcpy(¶ms, input.data(), input.size());
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LOG_INFO(Service_NVDRV, "called, mask=0x{:X}, mask_buf_addr=0x{:X}", params.mask_buf_size,
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LOG_DEBUG(Service_NVDRV, "called, mask_buffer_size=0x{:X}", params.mask_buffer_size);
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params.mask_buf_addr);
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if (params.mask_buffer_size != 0) {
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// TODO(ogniK): Confirm value on hardware
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params.tcp_mask = 3;
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if (params.mask_buf_size)
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}
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params.tpc_mask_size = 4 * 1; // 4 * num_gpc
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else
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if (version == IoctlVersion::Version3) {
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params.tpc_mask_size = 0;
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std::memcpy(output.data(), input.data(), output.size());
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std::memcpy(output.data(), ¶ms, sizeof(params));
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std::memcpy(output2.data(), ¶ms.tcp_mask, output2.size());
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} else {
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std::memcpy(output.data(), ¶ms, output.size());
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}
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return 0;
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return 0;
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}
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}
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@ -92,16 +92,11 @@ private:
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"IoctlCharacteristics is incorrect size");
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"IoctlCharacteristics is incorrect size");
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struct IoctlGpuGetTpcMasksArgs {
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struct IoctlGpuGetTpcMasksArgs {
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/// [in] TPC mask buffer size reserved by userspace. Should be at least
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u32_le mask_buffer_size{};
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/// sizeof(__u32) * fls(gpc_mask) to receive TPC mask for each GPC.
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INSERT_PADDING_WORDS(1);
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/// [out] full kernel buffer size
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u64_le mask_buffer_address{};
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u32_le mask_buf_size;
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u32_le tcp_mask{};
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u32_le reserved;
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INSERT_PADDING_WORDS(1);
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/// [in] pointer to TPC mask buffer. It will receive one 32-bit TPC mask per GPC or 0 if
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/// GPC is not enabled or not present. This parameter is ignored if mask_buf_size is 0.
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u64_le mask_buf_addr;
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u64_le tpc_mask_size; // Nintendo add this?
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};
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};
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static_assert(sizeof(IoctlGpuGetTpcMasksArgs) == 24,
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static_assert(sizeof(IoctlGpuGetTpcMasksArgs) == 24,
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"IoctlGpuGetTpcMasksArgs is incorrect size");
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"IoctlGpuGetTpcMasksArgs is incorrect size");
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@ -166,7 +161,8 @@ private:
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u32 GetCharacteristics(const std::vector<u8>& input, std::vector<u8>& output,
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u32 GetCharacteristics(const std::vector<u8>& input, std::vector<u8>& output,
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std::vector<u8>& output2, IoctlVersion version);
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std::vector<u8>& output2, IoctlVersion version);
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u32 GetTPCMasks(const std::vector<u8>& input, std::vector<u8>& output);
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u32 GetTPCMasks(const std::vector<u8>& input, std::vector<u8>& output, std::vector<u8>& output2,
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IoctlVersion version);
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u32 GetActiveSlotMask(const std::vector<u8>& input, std::vector<u8>& output);
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u32 GetActiveSlotMask(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZCullGetInfo(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZCullGetInfo(const std::vector<u8>& input, std::vector<u8>& output);
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