mirror of
https://github.com/yuzu-emu/yuzu-android.git
synced 2024-11-26 13:15:42 +01:00
Merge pull request #4973 from ameerj/nvdec-opt
nvdec: Reuse allocated buffers and general cleanup
This commit is contained in:
bunnei
GitHub
commit
9cae3e6e90
@ -34,8 +34,7 @@ NvResult nvhost_nvdec::Ioctl1(Ioctl command, const std::vector<u8>& input,
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case 0xa: {
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if (command.length == 0x1c) {
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LOG_INFO(Service_NVDRV, "NVDEC video stream ended");
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Tegra::ChCommandHeaderList cmdlist(1);
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cmdlist[0] = Tegra::ChCommandHeader{0xDEADB33F};
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Tegra::ChCommandHeaderList cmdlist{{0xDEADB33F}};
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system.GPU().PushCommandBuffer(cmdlist);
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}
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return UnmapBuffer(input, output);
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@ -28,8 +28,13 @@ NvResult nvhost_vic::Ioctl1(Ioctl command, const std::vector<u8>& input, std::ve
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return GetWaitbase(input, output);
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case 0x9:
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return MapBuffer(input, output);
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case 0xa:
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case 0xa: {
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if (command.length == 0x1c) {
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Tegra::ChCommandHeaderList cmdlist{{0xDEADB33F}};
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system.GPU().PushCommandBuffer(cmdlist);
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}
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return UnmapBuffer(input, output);
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}
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default:
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break;
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}
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@ -37,59 +37,43 @@ CDmaPusher::CDmaPusher(GPU& gpu_)
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CDmaPusher::~CDmaPusher() = default;
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void CDmaPusher::Push(ChCommandHeaderList&& entries) {
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cdma_queue.push(std::move(entries));
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}
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void CDmaPusher::DispatchCalls() {
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while (!cdma_queue.empty()) {
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Step();
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}
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}
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void CDmaPusher::Step() {
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const auto entries{cdma_queue.front()};
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cdma_queue.pop();
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std::vector<u32> values(entries.size());
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std::memcpy(values.data(), entries.data(), entries.size() * sizeof(u32));
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for (const u32 value : values) {
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void CDmaPusher::ProcessEntries(ChCommandHeaderList&& entries) {
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for (const auto& value : entries) {
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if (mask != 0) {
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const auto lbs = static_cast<u32>(std::countr_zero(mask));
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mask &= ~(1U << lbs);
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ExecuteCommand(static_cast<u32>(offset + lbs), value);
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ExecuteCommand(offset + lbs, value.raw);
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continue;
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} else if (count != 0) {
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--count;
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ExecuteCommand(static_cast<u32>(offset), value);
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ExecuteCommand(offset, value.raw);
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if (incrementing) {
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++offset;
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}
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continue;
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}
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const auto mode = static_cast<ChSubmissionMode>((value >> 28) & 0xf);
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const auto mode = value.submission_mode.Value();
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switch (mode) {
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case ChSubmissionMode::SetClass: {
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mask = value & 0x3f;
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offset = (value >> 16) & 0xfff;
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current_class = static_cast<ChClassId>((value >> 6) & 0x3ff);
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mask = value.value & 0x3f;
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offset = value.method_offset;
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current_class = static_cast<ChClassId>((value.value >> 6) & 0x3ff);
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break;
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}
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case ChSubmissionMode::Incrementing:
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case ChSubmissionMode::NonIncrementing:
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count = value & 0xffff;
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offset = (value >> 16) & 0xfff;
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count = value.value;
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offset = value.method_offset;
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incrementing = mode == ChSubmissionMode::Incrementing;
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break;
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case ChSubmissionMode::Mask:
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mask = value & 0xffff;
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offset = (value >> 16) & 0xfff;
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mask = value.value;
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offset = value.method_offset;
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break;
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case ChSubmissionMode::Immediate: {
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const u32 data = value & 0xfff;
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offset = (value >> 16) & 0xfff;
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ExecuteCommand(static_cast<u32>(offset), data);
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const u32 data = value.value & 0xfff;
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offset = value.method_offset;
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ExecuteCommand(offset, data);
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break;
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}
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default:
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@ -102,8 +86,8 @@ void CDmaPusher::Step() {
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void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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switch (current_class) {
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case ChClassId::NvDec:
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ThiStateWrite(nvdec_thi_state, state_offset, {data});
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switch (static_cast<ThiMethod>(state_offset)) {
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ThiStateWrite(nvdec_thi_state, offset, data);
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switch (static_cast<ThiMethod>(offset)) {
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case ThiMethod::IncSyncpt: {
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LOG_DEBUG(Service_NVDRV, "NVDEC Class IncSyncpt Method");
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const auto syncpoint_id = static_cast<u32>(data & 0xFF);
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@ -120,7 +104,7 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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LOG_DEBUG(Service_NVDRV, "NVDEC method 0x{:X}",
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static_cast<u32>(nvdec_thi_state.method_0));
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nvdec_processor->ProcessMethod(static_cast<Nvdec::Method>(nvdec_thi_state.method_0),
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{data});
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data);
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break;
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default:
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break;
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@ -144,7 +128,7 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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case ThiMethod::SetMethod1:
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LOG_DEBUG(Service_NVDRV, "VIC method 0x{:X}, Args=({})",
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static_cast<u32>(vic_thi_state.method_0), data);
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vic_processor->ProcessMethod(static_cast<Vic::Method>(vic_thi_state.method_0), {data});
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vic_processor->ProcessMethod(static_cast<Vic::Method>(vic_thi_state.method_0), data);
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break;
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default:
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break;
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@ -153,7 +137,7 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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case ChClassId::Host1x:
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// This device is mainly for syncpoint synchronization
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LOG_DEBUG(Service_NVDRV, "Host1X Class Method");
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host1x_processor->ProcessMethod(static_cast<Host1x::Method>(state_offset), {data});
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host1x_processor->ProcessMethod(static_cast<Host1x::Method>(offset), data);
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break;
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default:
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UNIMPLEMENTED_MSG("Current class not implemented {:X}", static_cast<u32>(current_class));
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@ -161,10 +145,9 @@ void CDmaPusher::ExecuteCommand(u32 state_offset, u32 data) {
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}
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}
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void CDmaPusher::ThiStateWrite(ThiRegisters& state, u32 state_offset,
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const std::vector<u32>& arguments) {
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u8* const state_offset_ptr = reinterpret_cast<u8*>(&state) + sizeof(u32) * state_offset;
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std::memcpy(state_offset_ptr, arguments.data(), sizeof(u32) * arguments.size());
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void CDmaPusher::ThiStateWrite(ThiRegisters& state, u32 state_offset, u32 argument) {
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u8* const offset_ptr = reinterpret_cast<u8*>(&state) + sizeof(u32) * state_offset;
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std::memcpy(offset_ptr, &argument, sizeof(u32));
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}
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} // namespace Tegra
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@ -5,9 +5,7 @@
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#pragma once
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#include <memory>
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#include <unordered_map>
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#include <vector>
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#include <queue>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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@ -16,9 +14,9 @@
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namespace Tegra {
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class GPU;
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class Host1x;
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class Nvdec;
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class Vic;
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class Host1x;
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enum class ChSubmissionMode : u32 {
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SetClass = 0,
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@ -48,16 +46,10 @@ enum class ChClassId : u32 {
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NvDec = 0xf0
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};
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enum class ChMethod : u32 {
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Empty = 0,
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SetMethod = 0x10,
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SetData = 0x11,
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};
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union ChCommandHeader {
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u32 raw;
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BitField<0, 16, u32> value;
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BitField<16, 12, ChMethod> method_offset;
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BitField<16, 12, u32> method_offset;
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BitField<28, 4, ChSubmissionMode> submission_mode;
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};
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static_assert(sizeof(ChCommandHeader) == sizeof(u32), "ChCommand header is an invalid size");
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@ -99,21 +91,15 @@ public:
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explicit CDmaPusher(GPU& gpu_);
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~CDmaPusher();
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/// Push NVDEC command buffer entries into queue
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void Push(ChCommandHeaderList&& entries);
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/// Process queued command buffer entries
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void DispatchCalls();
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/// Process one queue element
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void Step();
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/// Process the command entry
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void ProcessEntries(ChCommandHeaderList&& entries);
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private:
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/// Invoke command class devices to execute the command based on the current state
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void ExecuteCommand(u32 state_offset, u32 data);
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private:
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/// Write arguments value to the ThiRegisters member at the specified offset
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void ThiStateWrite(ThiRegisters& state, u32 state_offset, const std::vector<u32>& arguments);
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void ThiStateWrite(ThiRegisters& state, u32 offset, u32 argument);
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GPU& gpu;
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std::shared_ptr<Tegra::Nvdec> nvdec_processor;
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@ -124,13 +110,10 @@ private:
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ThiRegisters vic_thi_state{};
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ThiRegisters nvdec_thi_state{};
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s32 count{};
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s32 offset{};
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u32 count{};
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u32 offset{};
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u32 mask{};
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bool incrementing{};
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// Queue of command lists to be processed
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std::queue<ChCommandHeaderList> cdma_queue;
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};
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} // namespace Tegra
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@ -44,9 +44,11 @@ Codec::~Codec() {
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}
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void Codec::SetTargetCodec(NvdecCommon::VideoCodec codec) {
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LOG_INFO(Service_NVDRV, "NVDEC video codec initialized to {}", codec);
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if (current_codec != codec) {
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LOG_INFO(Service_NVDRV, "NVDEC video codec initialized to {}", static_cast<u32>(codec));
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current_codec = codec;
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}
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}
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void Codec::StateWrite(u32 offset, u64 arguments) {
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u8* const state_offset = reinterpret_cast<u8*>(&state) + offset * sizeof(u64);
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@ -55,7 +57,6 @@ void Codec::StateWrite(u32 offset, u64 arguments) {
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void Codec::Decode() {
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bool is_first_frame = false;
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if (!initialized) {
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if (current_codec == NvdecCommon::VideoCodec::H264) {
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av_codec = avcodec_find_decoder(AV_CODEC_ID_H264);
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@ -12,16 +12,16 @@ Nvdec::Nvdec(GPU& gpu_) : gpu(gpu_), codec(std::make_unique<Codec>(gpu)) {}
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Nvdec::~Nvdec() = default;
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void Nvdec::ProcessMethod(Method method, const std::vector<u32>& arguments) {
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void Nvdec::ProcessMethod(Method method, u32 argument) {
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if (method == Method::SetVideoCodec) {
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codec->StateWrite(static_cast<u32>(method), arguments[0]);
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codec->StateWrite(static_cast<u32>(method), argument);
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} else {
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codec->StateWrite(static_cast<u32>(method), static_cast<u64>(arguments[0]) << 8);
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codec->StateWrite(static_cast<u32>(method), static_cast<u64>(argument) << 8);
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}
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switch (method) {
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case Method::SetVideoCodec:
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codec->SetTargetCodec(static_cast<NvdecCommon::VideoCodec>(arguments[0]));
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codec->SetTargetCodec(static_cast<NvdecCommon::VideoCodec>(argument));
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break;
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case Method::Execute:
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Execute();
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@ -23,7 +23,7 @@ public:
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~Nvdec();
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/// Writes the method into the state, Invoke Execute() if encountered
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void ProcessMethod(Method method, const std::vector<u32>& arguments);
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void ProcessMethod(Method method, u32 argument);
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/// Return most recently decoded frame
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[[nodiscard]] AVFramePtr GetFrame();
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@ -18,18 +18,14 @@ extern "C" {
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namespace Tegra {
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Vic::Vic(GPU& gpu_, std::shared_ptr<Nvdec> nvdec_processor_)
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: gpu(gpu_), nvdec_processor(std::move(nvdec_processor_)) {}
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: gpu(gpu_),
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nvdec_processor(std::move(nvdec_processor_)), converted_frame_buffer{nullptr, av_free} {}
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Vic::~Vic() = default;
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void Vic::VicStateWrite(u32 offset, u32 arguments) {
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u8* const state_offset = reinterpret_cast<u8*>(&vic_state) + offset * sizeof(u32);
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std::memcpy(state_offset, &arguments, sizeof(u32));
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}
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void Vic::ProcessMethod(Method method, const std::vector<u32>& arguments) {
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LOG_DEBUG(HW_GPU, "Vic method 0x{:X}", method);
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VicStateWrite(static_cast<u32>(method), arguments[0]);
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const u64 arg = static_cast<u64>(arguments[0]) << 8;
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void Vic::ProcessMethod(Method method, u32 argument) {
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LOG_DEBUG(HW_GPU, "Vic method 0x{:X}", static_cast<u32>(method));
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const u64 arg = static_cast<u64>(argument) << 8;
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switch (method) {
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case Method::Execute:
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Execute();
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@ -53,8 +49,7 @@ void Vic::ProcessMethod(Method method, const std::vector<u32>& arguments) {
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void Vic::Execute() {
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if (output_surface_luma_address == 0) {
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LOG_ERROR(Service_NVDRV, "VIC Luma address not set. Received 0x{:X}",
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vic_state.output_surface.luma_offset);
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LOG_ERROR(Service_NVDRV, "VIC Luma address not set.");
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return;
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}
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const VicConfig config{gpu.MemoryManager().Read<u64>(config_struct_address + 0x20)};
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@ -89,8 +84,10 @@ void Vic::Execute() {
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// Get Converted frame
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const std::size_t linear_size = frame->width * frame->height * 4;
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using AVMallocPtr = std::unique_ptr<u8, decltype(&av_free)>;
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AVMallocPtr converted_frame_buffer{static_cast<u8*>(av_malloc(linear_size)), av_free};
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// Only allocate frame_buffer once per stream, as the size is not expected to change
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if (!converted_frame_buffer) {
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converted_frame_buffer = AVMallocPtr{static_cast<u8*>(av_malloc(linear_size)), av_free};
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}
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const int converted_stride{frame->width * 4};
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u8* const converted_frame_buf_addr{converted_frame_buffer.get()};
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@ -104,12 +101,12 @@ void Vic::Execute() {
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const u32 block_height = static_cast<u32>(config.block_linear_height_log2);
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const auto size = Tegra::Texture::CalculateSize(true, 4, frame->width, frame->height, 1,
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block_height, 0);
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std::vector<u8> swizzled_data(size);
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luma_buffer.resize(size);
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Tegra::Texture::SwizzleSubrect(frame->width, frame->height, frame->width * 4,
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frame->width, 4, swizzled_data.data(),
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frame->width, 4, luma_buffer.data(),
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converted_frame_buffer.get(), block_height, 0, 0);
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gpu.MemoryManager().WriteBlock(output_surface_luma_address, swizzled_data.data(), size);
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gpu.MemoryManager().WriteBlock(output_surface_luma_address, luma_buffer.data(), size);
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} else {
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// send pitch linear frame
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gpu.MemoryManager().WriteBlock(output_surface_luma_address, converted_frame_buf_addr,
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@ -132,15 +129,15 @@ void Vic::Execute() {
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const auto stride = frame->linesize[0];
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const auto half_stride = frame->linesize[1];
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std::vector<u8> luma_buffer(aligned_width * surface_height);
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std::vector<u8> chroma_buffer(aligned_width * half_height);
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luma_buffer.resize(aligned_width * surface_height);
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chroma_buffer.resize(aligned_width * half_height);
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// Populate luma buffer
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for (std::size_t y = 0; y < surface_height - 1; ++y) {
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std::size_t src = y * stride;
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std::size_t dst = y * aligned_width;
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const std::size_t src = y * stride;
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const std::size_t dst = y * aligned_width;
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std::size_t size = surface_width;
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const std::size_t size = surface_width;
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for (std::size_t offset = 0; offset < size; ++offset) {
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luma_buffer[dst + offset] = luma_ptr[src + offset];
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@ -151,8 +148,8 @@ void Vic::Execute() {
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// Populate chroma buffer from both channels with interleaving.
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for (std::size_t y = 0; y < half_height; ++y) {
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std::size_t src = y * half_stride;
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std::size_t dst = y * aligned_width;
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const std::size_t src = y * half_stride;
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const std::size_t dst = y * aligned_width;
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for (std::size_t x = 0; x < half_width; ++x) {
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chroma_buffer[dst + x * 2] = chroma_b_ptr[src + x];
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@ -15,43 +15,6 @@ namespace Tegra {
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class GPU;
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class Nvdec;
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struct PlaneOffsets {
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u32 luma_offset{};
|
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u32 chroma_u_offset{};
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u32 chroma_v_offset{};
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};
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struct VicRegisters {
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INSERT_PADDING_WORDS(64);
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u32 nop{};
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INSERT_PADDING_WORDS(15);
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u32 pm_trigger{};
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INSERT_PADDING_WORDS(47);
|
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u32 set_application_id{};
|
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u32 set_watchdog_timer{};
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INSERT_PADDING_WORDS(17);
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u32 context_save_area{};
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u32 context_switch{};
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INSERT_PADDING_WORDS(43);
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u32 execute{};
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INSERT_PADDING_WORDS(63);
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std::array<std::array<PlaneOffsets, 8>, 8> surfacex_slots{};
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u32 picture_index{};
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u32 control_params{};
|
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u32 config_struct_offset{};
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u32 filter_struct_offset{};
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u32 palette_offset{};
|
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u32 hist_offset{};
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u32 context_id{};
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u32 fce_ucode_size{};
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PlaneOffsets output_surface{};
|
||||
u32 fce_ucode_offset{};
|
||||
INSERT_PADDING_WORDS(4);
|
||||
std::array<u32, 8> slot_context_id{};
|
||||
INSERT_PADDING_WORDS(16);
|
||||
};
|
||||
static_assert(sizeof(VicRegisters) == 0x7A0, "VicRegisters is an invalid size");
|
||||
|
||||
class Vic {
|
||||
public:
|
||||
enum class Method : u32 {
|
||||
@ -67,14 +30,11 @@ public:
|
||||
~Vic();
|
||||
|
||||
/// Write to the device state.
|
||||
void ProcessMethod(Method method, const std::vector<u32>& arguments);
|
||||
void ProcessMethod(Method method, u32 argument);
|
||||
|
||||
private:
|
||||
void Execute();
|
||||
|
||||
void VicStateWrite(u32 offset, u32 arguments);
|
||||
VicRegisters vic_state{};
|
||||
|
||||
enum class VideoPixelFormat : u64_le {
|
||||
RGBA8 = 0x1f,
|
||||
BGRA8 = 0x20,
|
||||
@ -88,8 +48,6 @@ private:
|
||||
BitField<9, 2, u64_le> chroma_loc_vert;
|
||||
BitField<11, 4, u64_le> block_linear_kind;
|
||||
BitField<15, 4, u64_le> block_linear_height_log2;
|
||||
BitField<19, 3, u64_le> reserved0;
|
||||
BitField<22, 10, u64_le> reserved1;
|
||||
BitField<32, 14, u64_le> surface_width_minus1;
|
||||
BitField<46, 14, u64_le> surface_height_minus1;
|
||||
};
|
||||
@ -97,6 +55,13 @@ private:
|
||||
GPU& gpu;
|
||||
std::shared_ptr<Tegra::Nvdec> nvdec_processor;
|
||||
|
||||
/// Avoid reallocation of the following buffers every frame, as their
|
||||
/// size does not change during a stream
|
||||
using AVMallocPtr = std::unique_ptr<u8, decltype(&av_free)>;
|
||||
AVMallocPtr converted_frame_buffer;
|
||||
std::vector<u8> luma_buffer;
|
||||
std::vector<u8> chroma_buffer;
|
||||
|
||||
GPUVAddr config_struct_address{};
|
||||
GPUVAddr output_surface_luma_address{};
|
||||
GPUVAddr output_surface_chroma_u_address{};
|
||||
|
||||
@ -30,8 +30,7 @@ MICROPROFILE_DEFINE(GPU_wait, "GPU", "Wait for the GPU", MP_RGB(128, 128, 192));
|
||||
|
||||
GPU::GPU(Core::System& system_, bool is_async_, bool use_nvdec_)
|
||||
: system{system_}, memory_manager{std::make_unique<Tegra::MemoryManager>(system)},
|
||||
dma_pusher{std::make_unique<Tegra::DmaPusher>(system, *this)},
|
||||
cdma_pusher{std::make_unique<Tegra::CDmaPusher>(*this)}, use_nvdec{use_nvdec_},
|
||||
dma_pusher{std::make_unique<Tegra::DmaPusher>(system, *this)}, use_nvdec{use_nvdec_},
|
||||
maxwell_3d{std::make_unique<Engines::Maxwell3D>(system, *memory_manager)},
|
||||
fermi_2d{std::make_unique<Engines::Fermi2D>()},
|
||||
kepler_compute{std::make_unique<Engines::KeplerCompute>(system, *memory_manager)},
|
||||
@ -494,8 +493,7 @@ void GPU::PushCommandBuffer(Tegra::ChCommandHeaderList& entries) {
|
||||
// TODO(ameerj): RE proper async nvdec operation
|
||||
// gpu_thread.SubmitCommandBuffer(std::move(entries));
|
||||
|
||||
cdma_pusher->Push(std::move(entries));
|
||||
cdma_pusher->DispatchCalls();
|
||||
cdma_pusher->ProcessEntries(std::move(entries));
|
||||
}
|
||||
|
||||
void GPU::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
|
||||
|
||||
@ -48,8 +48,7 @@ static void RunThread(Core::System& system, VideoCore::RendererBase& renderer,
|
||||
dma_pusher.DispatchCalls();
|
||||
} else if (auto* command_list = std::get_if<SubmitChCommandEntries>(&next.data)) {
|
||||
// NVDEC
|
||||
cdma_pusher.Push(std::move(command_list->entries));
|
||||
cdma_pusher.DispatchCalls();
|
||||
cdma_pusher.ProcessEntries(std::move(command_list->entries));
|
||||
} else if (const auto* data = std::get_if<SwapBuffersCommand>(&next.data)) {
|
||||
renderer.SwapBuffers(data->framebuffer ? &*data->framebuffer : nullptr);
|
||||
} else if (std::holds_alternative<OnCommandListEndCommand>(next.data)) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user