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Merge pull request #283 from Subv/tsc
GPU: Added sampler information structures (TSC)
This commit is contained in:
commit
f934da0e43
@ -294,8 +294,45 @@ void Maxwell3D::ProcessCBData(u32 value) {
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regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
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}
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std::vector<Texture::TICEntry> Maxwell3D::GetStageTextures(Regs::ShaderStage stage) {
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std::vector<Texture::TICEntry> textures;
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Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
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GPUVAddr tic_base_address = regs.tic.TICAddress();
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GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
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VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
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Texture::TICEntry tic_entry;
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Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
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ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear,
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"TIC versions other than BlockLinear are unimplemented");
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ASSERT_MSG(tic_entry.texture_type == Texture::TextureType::Texture2D,
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"Texture types other than Texture2D are unimplemented");
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auto r_type = tic_entry.r_type.Value();
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auto g_type = tic_entry.g_type.Value();
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auto b_type = tic_entry.b_type.Value();
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auto a_type = tic_entry.a_type.Value();
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// TODO(Subv): Different data types for separate components are not supported
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ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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return tic_entry;
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}
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Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
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GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
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GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
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VAddr tsc_address_cpu = memory_manager.PhysicalToVirtualAddress(tsc_address_gpu);
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Texture::TSCEntry tsc_entry;
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Memory::ReadBlock(tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
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return tsc_entry;
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}
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std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderStage stage) const {
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std::vector<Texture::FullTextureInfo> textures;
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auto& fragment_shader = state.shader_stages[static_cast<size_t>(stage)];
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auto& tex_info_buffer = fragment_shader.const_buffers[regs.tex_cb_index];
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@ -309,31 +346,34 @@ std::vector<Texture::TICEntry> Maxwell3D::GetStageTextures(Regs::ShaderStage sta
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static constexpr size_t TextureInfoOffset = 0x20;
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for (GPUVAddr current_texture = tex_info_buffer.address + TextureInfoOffset;
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current_texture < tex_info_buffer_end; current_texture += 4) {
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current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
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Texture::TextureHandle tex_info{
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Texture::TextureHandle tex_handle{
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Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))};
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if (tex_info.tic_id != 0 || tex_info.tsc_id != 0) {
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GPUVAddr tic_address_gpu =
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tic_base_address + tex_info.tic_id * sizeof(Texture::TICEntry);
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VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
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Texture::FullTextureInfo tex_info{};
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// TODO(Subv): Use the shader to determine which textures are actually accessed.
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tex_info.index = (current_texture - tex_info_buffer.address - TextureInfoOffset) /
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sizeof(Texture::TextureHandle);
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Texture::TICEntry tic_entry;
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Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
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// Load the TIC data.
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if (tex_handle.tic_id != 0) {
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tex_info.enabled = true;
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auto r_type = tic_entry.r_type.Value();
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auto g_type = tic_entry.g_type.Value();
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auto b_type = tic_entry.b_type.Value();
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auto a_type = tic_entry.a_type.Value();
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// TODO(Subv): Different data types for separate components are not supported
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ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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auto format = tic_entry.format.Value();
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textures.push_back(tic_entry);
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auto tic_entry = GetTICEntry(tex_handle.tic_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
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}
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// Load the TSC data
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if (tex_handle.tsc_id != 0) {
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auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
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// TODO(Subv): Workaround for BitField's move constructor being deleted.
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std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
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}
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if (tex_info.enabled)
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textures.push_back(tex_info);
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}
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return textures;
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@ -432,7 +432,7 @@ public:
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void SubmitMacroCode(u32 entry, std::vector<u32> code);
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/// Returns a list of enabled textures for the specified shader stage.
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std::vector<Texture::TICEntry> GetStageTextures(Regs::ShaderStage stage);
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std::vector<Texture::FullTextureInfo> GetStageTextures(Regs::ShaderStage stage) const;
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private:
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MemoryManager& memory_manager;
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@ -444,6 +444,12 @@ private:
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/// Parameters that have been submitted to the macro call so far.
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std::vector<u32> macro_params;
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/// Retrieves information about a specific TIC entry from the TIC buffer.
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Texture::TICEntry GetTICEntry(u32 tic_index) const;
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/// Retrieves information about a specific TSC entry from the TSC buffer.
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Texture::TSCEntry GetTSCEntry(u32 tsc_index) const;
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/**
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* Call a macro on this engine.
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* @param method Method to call
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@ -17,11 +17,32 @@ enum class TextureFormat : u32 {
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DXT1 = 0x24,
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};
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enum class TextureType : u32 {
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Texture1D = 0,
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Texture2D = 1,
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Texture3D = 2,
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TextureCubemap = 3,
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Texture1DArray = 4,
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Texture2DArray = 5,
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Texture1DBuffer = 6,
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Texture2DNoMipmap = 7,
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TextureCubeArray = 8,
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};
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enum class TICHeaderVersion : u32 {
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OneDBuffer = 0,
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PitchColorKey = 1,
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Pitch = 2,
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BlockLinear = 3,
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BlockLinearColorKey = 4,
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};
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union TextureHandle {
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u32 raw;
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BitField<0, 20, u32> tic_id;
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BitField<20, 12, u32> tsc_id;
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};
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static_assert(sizeof(TextureHandle) == 4, "TextureHandle has wrong size");
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struct TICEntry {
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union {
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@ -33,10 +54,15 @@ struct TICEntry {
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BitField<16, 3, u32> a_type;
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};
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u32 address_low;
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u16 address_high;
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INSERT_PADDING_BYTES(6);
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u16 width_minus_1;
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INSERT_PADDING_BYTES(2);
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union {
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BitField<0, 16, u32> address_high;
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BitField<21, 3, TICHeaderVersion> header_version;
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};
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INSERT_PADDING_BYTES(4);
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union {
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BitField<0, 16, u32> width_minus_1;
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BitField<23, 4, TextureType> texture_type;
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};
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u16 height_minus_1;
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INSERT_PADDING_BYTES(10);
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@ -54,6 +80,56 @@ struct TICEntry {
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};
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static_assert(sizeof(TICEntry) == 0x20, "TICEntry has wrong size");
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enum class WrapMode : u32 {
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Wrap = 0,
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Mirror = 1,
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ClampToEdge = 2,
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Border = 3,
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ClampOGL = 4,
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MirrorOnceClampToEdge = 5,
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MirrorOnceBorder = 6,
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MirrorOnceClampOGL = 7,
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};
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enum class TextureFilter : u32 {
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Nearest = 1,
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Linear = 2,
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};
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enum class TextureMipmapFilter : u32 {
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None = 1,
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Nearest = 2,
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Linear = 3,
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};
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struct TSCEntry {
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union {
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BitField<0, 3, WrapMode> wrap_u;
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BitField<3, 3, WrapMode> wrap_v;
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BitField<6, 3, WrapMode> wrap_p;
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BitField<9, 1, u32> depth_compare_enabled;
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BitField<10, 3, u32> depth_compare_func;
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};
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union {
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BitField<0, 2, TextureFilter> mag_filter;
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BitField<4, 2, TextureFilter> min_filter;
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BitField<6, 2, TextureMipmapFilter> mip_filter;
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};
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INSERT_PADDING_BYTES(8);
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u32 border_color_r;
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u32 border_color_g;
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u32 border_color_b;
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u32 border_color_a;
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};
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static_assert(sizeof(TSCEntry) == 0x20, "TSCEntry has wrong size");
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struct FullTextureInfo {
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u32 index;
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TICEntry tic;
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TSCEntry tsc;
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bool enabled;
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};
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/// Returns the number of bytes per pixel of the input texture format.
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u32 BytesPerPixel(TextureFormat format);
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